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i965: ff sync message change for sandybridge
2010-09-28
Zhenyu Wang
i965: ff sync message change for sandybridge
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2010-09-28
Zhenyu Wang
i965: fix point size setting in header on sandybridge
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2010-09-28
Zhenyu Wang
i965: force zero in clipper to ignore RTAIndex on sandybridge
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2010-09-28
Zhenyu Wang
i965: Fix color interpolation on sandybridge
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2010-09-28
Zhenyu Wang
i965: enable accumulator update in PS kernel too on...
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2010-09-28
Zhenyu Wang
i965: new state dump for sandybridge
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2010-09-28
Zhenyu Wang
i965: disasm quarter and write enable instruction control...
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2010-08-31
Zhenyu Wang
i965: fix depth test on sandybridge
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2010-08-23
Zhenyu Wang
i965: Add sandybridge D0 pci ids
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2010-08-20
Zhenyu Wang
i965: Add support for FB writes on Sandybridge.
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2010-08-20
Zhenyu Wang
i965: Set the destination horiz stride even for da16...
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2010-08-20
Zhenyu Wang
i965: Set the maximum number of threads on Sandybridge.
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2010-08-20
Zhenyu Wang
i965: Add AccWrCtl support on Sandybridge.
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2010-08-20
Zhenyu Wang
i965: Mention the mlen and rlen for URB reads.
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2010-08-20
Zhenyu Wang
i965: Sandybridge doesn't have Compr4 mode, since it...
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2010-08-20
Zhenyu Wang
i965: Adjust disasm of subreg numbers to be in units...
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2010-07-08
Zhenyu Wang
i965: Add 'wait' instruction support
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2010-07-08
Zhenyu Wang
i965: Add decode for Sandybridge DP write messages.
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2010-07-08
Zhenyu Wang
i965: Add definitions for Sandybridge DP write/read...
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2010-06-14
Zhenyu Wang
i965: correct the gen6 line stipple enable define.
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2010-06-13
Zhenyu Wang
i965: Use the new message header format for FF_SYNC...
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2010-06-13
Zhenyu Wang
i965: Add support for math instructions in the gen6 WM.
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2010-06-13
Zhenyu Wang
i965: Set the correct WM GRF start reg on gen6.
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2010-04-21
Zhenyu Wang
intel: Add Sandybridge mobile chipset id
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2010-04-21
Zhenyu Wang
intel: Clean up chipset name and gen num for Ironlake
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2009-09-10
Zhenyu Wang
intel: add B43 chipset support
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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2009-09-09
Zhenyu Wang
intel: add B43 chipset support
Signed-off-by:
Zhenyu Wang
<zhenyuw@linux.intel.com>
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