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re PR target/60697 ([aarch64] LRA ICE (Segfault) while building 435.gromacs)
2014-03-24
Alex Velenko
[AArch64] Logical vector shift right conformance
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2014-02-06
Alex Velenko
[AArch64] Shift right pattern fix
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2014-01-23
Alex Velenko
[PATCH][AArch64] Vector shift by 64 fix
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2014-01-23
Alex Velenko
[AArch64_BE 2/4] Big-Endian lane numbering fix
2013-01-23
Alex Velenko
<Alex.Velenko@arm.com>
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2014-01-23
Alex Velenko
[AArch64_BE 1/4] Big-Endian lane numbering fix
2014-01-23
Alex Velenko
<Alex.Velenko@arm.com>
2014-01-23
Alex Velenko
<Alex.Velenko@arm.com>
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2014-01-20
Alex Velenko
[AArch64] Disable vec_perm patterns for aarch64_be.
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2014-01-20
Alex Velenko
[AArch64] vneg floating point testcase BE fixed.
2013-01-20
Alex Velenko
<Alex.Velenko@arm.com>
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2013-11-22
Alex Velenko
[AArch64] vmov_n changes
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2013-10-09
Alex Velenko
[AArch64] Implement vclz ADVSimd intrinsic.
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2013-10-09
Alex Velenko
[AArch64] Implement vadd_f64 and vsub_f64 ADVSimd intrinsics.
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2013-10-09
Alex Velenko
[AArch64] Implemented vdiv_f64 ADVSimd intrinsic.
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2013-10-09
Alex Velenko
[AArch64] vneg ADVSimd intrinsics rewritten in C.
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