git.libre-soc.org Git - yosys.git/search

2018-12-06	whitequark	synth_ice40: split `map_gates` off `fine`.	commit \| commitdiff \| tree
2018-12-05	whitequark	synth_ice40: add -noabc option, to use built-in LUT...	commit \| commitdiff \| tree
2018-12-05	whitequark	gate2lut: new techlib, for converting Yosys gates to...	commit \| commitdiff \| tree
2018-12-05	whitequark	Fix typo.	commit \| commitdiff \| tree
2018-12-05	whitequark	opt_lut: add -dlogic, to avoid disturbing logic such...	commit \| commitdiff \| tree
2018-12-05	whitequark	opt_lut: always prefer to eliminate 1-LUTs.	commit \| commitdiff \| tree
2018-12-05	whitequark	opt_lut: collect and display statistics.	commit \| commitdiff \| tree
2018-12-05	whitequark	opt_lut: refactor to use a worker. NFC.	commit \| commitdiff \| tree
2018-12-05	whitequark	synth_ice40: add -relut option, to run ice40_unlut...	commit \| commitdiff \| tree
2018-12-05	whitequark	opt_lut: new pass, to combine LUTs for tighter packing.	commit \| commitdiff \| tree
2018-12-05	whitequark	Extract ice40_unlut pass from ice40_opt.	commit \| commitdiff \| tree
2016-08-10	whitequark	synth_greenpak4: use attrmvcp to move LOC from wires...	commit \| commitdiff \| tree
2016-07-12	whitequark	write_json: also write module attributes.	commit \| commitdiff \| tree
2016-07-10	whitequark	greenpak4: add GP_COUNT{8,14}_ADV cells.	commit \| commitdiff \| tree