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tests: Using super in arm_generic whenever possible
2019-06-09
Giacomo Travaglini
base: Rename TestFiber into SwitchingFiber
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-06-07
Giacomo Travaglini
arch-arm: Fix WalkerState,Descriptors default constructor
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-24
Giacomo Travaglini
arch-arm: Fix fallthrough when trapping at EL2
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-23
Giacomo Travaglini
arch-arm: Trap virtual accesses to GICv3 SGI registers
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-23
Giacomo Travaglini
arch-arm: Expose haveGicv3CPUInterface to the ISA interface
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-23
Giacomo Travaglini
arch-arm: Change mcrMrc15TrapToHyp signature
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-22
Giacomo Travaglini
dev-arm: Provide a GICv3 ITS Implementation
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-14
Giacomo Travaglini
Revert "cpu: fix how a thread starts up in MinorCPU"
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-14
Giacomo Travaglini
Revert "cpu: stop scheduling suspended threads in MinorCPU"
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-14
Giacomo Travaglini
Revert "cpu: fix branching when thread is suspended...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-03
Giacomo Travaglini
dev: StreamID generation in DMA device
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: Store a PhysProxy port in Gicv3Redist
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: Add named variable for GICD_TYPER.IDBits
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: Read correct version of ICC_BPR register
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: Get a Gicv3Redistributor ptr from phys address
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Add several LPI methods in Gicv3Redistributor
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Take LPIs into account when interacting with...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Fix GICv3 LPIs priority value
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Disable LPI Configuration Table caching
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: Check EnableLPIs before checking for pending...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-05-02
Giacomo Travaglini
dev-arm: GICv3 LPI tables are using physical addresses
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Fix GICv3 LPI loop
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-05-02
Giacomo Travaglini
dev-arm: Fix Bitwise operation in GICv3
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-29
Giacomo Travaglini
arch-arm: Faults DebugFlag now printing inst opcode...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-29
Giacomo Travaglini
arch-arm: Report real instruction encoding when Undefined
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-26
Giacomo Travaglini
arch-arm: updateMiscReg not setting isHyp in aarch64
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
arch-arm: Remove un-needed hyp flag in TLBI operations
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
arch-arm: Correct target EL field in TLBI operations
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
dev-arm: Move GICv3 (Re)Ditributor address in Realview.py
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
dev-arm: Limit number of max PE in GICv3 to 128
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
dev-arm: Add GICv4 extension switch in GICv3
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-25
Giacomo Travaglini
dev-arm: Check for maximum number of supported PE in...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-11
Giacomo Travaglini
arch-arm: Enable PMSELR_EL0 read in PMU
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-10
Giacomo Travaglini
cpu: O3 switchFreeList checking VecElems instead of...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-04-02
Giacomo Travaglini
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-28
Giacomo Travaglini
arch-arm: Fix index generation for VecElem operands
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-27
Giacomo Travaglini
dev-arm: Rename GIC maintenance interrupt from ppint...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-27
Giacomo Travaglini
dev-arm: Fix GICv3 overflow for INTID > 256
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-27
Giacomo Travaglini
dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI ...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-26
Giacomo Travaglini
dev-arm: Set/Unset dma coherent mode from python
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-22
Giacomo Travaglini
base: Fix CircularQueue's operator-= when negative...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-03-22
Giacomo Travaglini
base: Fix CircularQueue when diffing iterators
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-01
Giacomo Travaglini
dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-03-01
Giacomo Travaglini
dev-arm: Set ICV_IGRPEN<n>_EL1-ICH_VMCR_EL2 mapping...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-18
Giacomo Travaglini
arch-arm: Move GICv3 detection at startup time
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-18
Giacomo Travaglini
base: Fix enums checkpointing
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-15
Giacomo Travaglini
cpu: Fix fast build broken due to unused variable
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-13
Giacomo Travaglini
configs: simpoint-profile usable with NonCachingCPUs...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-08
Giacomo Travaglini
arch-arm: Fix Virtual interrupts in AArch64
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-08
Giacomo Travaglini
arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d0483...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-02-08
Giacomo Travaglini
arch-arm: Allow ArmPPI usage for PMU
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-02-07
Giacomo Travaglini
configs, arch-arm: Using AddrRange for Realview mem_regions
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-02-07
Giacomo Travaglini
configs: Unifiy interpretation of Realview mem_regions
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-30
Giacomo Travaglini
configs: Enable DTB autogeneration in starter_fs.py
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-30
Giacomo Travaglini
arch-arm, configs: Create single instance of DTB autogeneration
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
arch-arm: Remove floatReg operand type
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
arch-arm: Use VecElem instead of FloatReg for FP instruction
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2019-01-25
Giacomo Travaglini
arch: Fix VecElem Operand generation in ISA parser
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
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2019-01-25
Giacomo Travaglini
cpu, arch, arch-arm: Wire unused VecElem code in the...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
cpu: O3 rename using the flatIndex instead of index
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
arch-arm: Inital vector rename mode depending on A32/A64
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2019-01-25
Giacomo Travaglini
cpu: Fix VecElemClass bugs in cpu models
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
cpu: Add VecElem entries in MinorCPU Scoreboard
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
arch-arm: Remove unused float operands
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-25
Giacomo Travaglini
arch: Provide traceback when parsing ISA code
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-23
Giacomo Travaglini
arch-arm: Implement LoadAcquire/StoreRelease in AArch32
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-23
Giacomo Travaglini
arch-arm: IsStoreConditional flag set depending on...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-23
Giacomo Travaglini
arch-arm: Remove SWP and SWPB instructions
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-22
Giacomo Travaglini
arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-16
Giacomo Travaglini
arch-arm: Read VMPIDR instead of MPIDR when EL2 is...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-15
Giacomo Travaglini
cpu: Fix usage of setArchVecElem
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-15
Giacomo Travaglini
arch-arm: Fix usage of RegId constructor for VecElem
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-10
Giacomo Travaglini
base: Make it possible to convert strings to enums
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-04
Giacomo Travaglini
dev-arm: Implement GIC-400 model from GicV2
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2019-01-04
Giacomo Travaglini
dev-arm: Move VGic from Realview.py to Gic.py
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-12-19
Giacomo Travaglini
arch-arm: Add Crypto in SE mode
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-12-08
Giacomo Travaglini
base, systemc: Fix clang compilation
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-12-07
Giacomo Travaglini
mem: Compile tracePacket only when TRACING_ON is defined
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-12-06
Giacomo Travaglini
ext: Build googlemock with googletest
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-12-06
Giacomo Travaglini
ext: Import googlemock, release version 1.8.0
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
>
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-28
Giacomo Travaglini
tests: Convert IniFile unit test to a GTest
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-14
Giacomo Travaglini
arch-arm: Print register name when warning on AT instructions
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-14
Giacomo Travaglini
sim: Move BitUnion overloading to show/parseParams
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-14
Giacomo Travaglini
sim: Move paramIn/Out definition to header file
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-12
Giacomo Travaglini
systemc: Push python headers on top of sources
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: Deprecate usage of legacy bootloader patching
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: ArmSystem::resetAddr64 renamed to be used...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: Implement AArch32 RVBAR
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: Remove SCTLR.VE bit
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: Refactor ISA::clear by adding a ISA::clear32...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-11-07
Giacomo Travaglini
arch-arm: Remove MISCREG commented numbers
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: IMPDEF for SYS instruction with CRn = {11...
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: Refactor AArch64 MSR/MRS trapping
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: Trap to EL2 only if not in Secure State
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: Fix HVC trapping beahviour
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-26
Giacomo Travaglini
arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-09
Giacomo Travaglini
arch-arm: Add have_crypto System parameter
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-09
Giacomo Travaglini
cpu: Fix MinorCPU executing Crypto Instructions
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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2018-10-09
Giacomo Travaglini
arch-arm: AArch64 Crypto AES
...off-by: Giacomo Travaglini <
giacomo.travaglini@arm.com
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