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ruby: MI protocol: add a missing transition
2013-01-31
Andreas Hansson
mem: Add comments for the DRAM address decoding
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2013-01-31
Andreas Hansson
stats: Update stats for regressions using SimpleDDR3
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2013-01-31
Andreas Hansson
mem: Add DDR3 and LPDDR2 DRAM controller configurations
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2013-01-31
Andreas Hansson
mem: Separate out the different cases for DRAM bus...
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2013-01-28
Andreas Hansson
stats: Fix naming (BPredUnit to branchPred) for 20...
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2013-01-21
Andreas Hansson
scons: Disable protobuf if pkg-config and CheckLib...
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2013-01-14
Andreas Hansson
scons: Address clang 3.2 compilation error
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2013-01-14
Andreas Hansson
stats: Bump failing x86 regression stats
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2013-01-07
Andreas Hansson
dev: Do not serialize timer parameters
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2013-01-07
Andreas Hansson
scons: Enforce gcc >= 4.4 or clang >= 2.9 and c++0x...
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2013-01-07
Andreas Hansson
scons: Remove stale compiler options
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2013-01-07
Andreas Hansson
sim: Fatal if a clocked object is set to have a clock...
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2013-01-07
Andreas Hansson
dev: Make the ethernet devices use a non-zero clock
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2013-01-07
Andreas Hansson
mem: Merge ranges that are part of the conf table
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2013-01-07
Andreas Hansson
base: Add support for merging of interleaved address...
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2013-01-07
Andreas Hansson
mem: Add interleaving bits to the address ranges
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2013-01-07
Andreas Hansson
config: Traverse lists when visiting children in all...
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2013-01-07
Andreas Hansson
base: Simplify the AddrRangeMap by removing unused...
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2013-01-07
Andreas Hansson
config: Do not use hardcoded physmem in fs script
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2013-01-07
Andreas Hansson
mem: Tidy up bus addr range debug messages
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2013-01-07
Andreas Hansson
mem: Skip address mapper range checks to allow more...
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2013-01-07
Andreas Hansson
base: Encapsulate the underlying fields in AddrRange
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2013-01-07
Andreas Hansson
mem: Remove the joining of neighbouring ranges
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2013-01-07
Andreas Hansson
cpu: Share the send functionality between traffic generators
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2013-01-07
Andreas Hansson
cpu: Add support for protobuf input for the trace generator
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2013-01-07
Andreas Hansson
cpu: Encapsulate traffic generator input in a stream
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2013-01-07
Andreas Hansson
base: Add wrapped protobuf input stream
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2013-01-07
Andreas Hansson
mem: Add tracing support in the communication monitor
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2013-01-07
Andreas Hansson
base: Add wrapped protobuf output streams
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2013-01-07
Andreas Hansson
scons: Add support for google protobuf building
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2013-01-07
Andreas Hansson
dev: Fix the Pl111 timings by separating pixel and...
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2013-01-07
Andreas Hansson
stats: Update DRAM regression stats to match new config
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2013-01-07
Andreas Hansson
config: Reduce DRAM controller regression traffic rate
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2013-01-07
Andreas Hansson
cpu: Fix the traffic gen read percentage
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2013-01-07
Andreas Hansson
mem: Add sanity check to packet queue size
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2013-01-07
Andreas Hansson
ruby: Fix missing cxx_header in Switch
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2013-01-07
Andreas Hansson
scons: Fix libelf linking errors when using clang/llvm
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2013-01-07
Andreas Hansson
mem: Fix a bug in the memory serialization file naming
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2012-11-19
Andreas Hansson
config: Fix description of checkpoint option from cycle...
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2012-11-08
Andreas Hansson
mem: Fix DRAM draining to ensure write queue is empty
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2012-10-31
Andreas Hansson
mem: Fix typo in port comments
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2012-10-31
Andreas Hansson
stats: Update stats for fixed simple-atomic-mp config
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2012-10-31
Andreas Hansson
config: Fix a typo in the simple-atomic-mp configuration
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2012-10-30
Andreas Hansson
stats: Update stats for unified cache configuration
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2012-10-30
Andreas Hansson
config: Unify caches used in regressions and adjust...
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2012-10-26
Andreas Hansson
config: Add a check for fastmem only used with Atomic CPU
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2012-10-26
Andreas Hansson
config: Remove unused mem_size in fs.py
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2012-10-26
Andreas Hansson
config: Fix the cache class naming in regression scripts
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2012-10-25
Andreas Hansson
stats: Update the stats to reflect the 1GHz default...
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2012-10-25
Andreas Hansson
dev: Make default clock more reasonable for system...
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2012-10-25
Andreas Hansson
stats: Update stats to reflect use of SimpleDRAM
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2012-10-25
Andreas Hansson
config: Use SimpleDRAM in full-system, and with o3...
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2012-10-25
Andreas Hansson
config: Use shared cache config for regressions
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2012-10-25
Andreas Hansson
arm: Use table walker clock that is inherited from CPU
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2012-10-23
Andreas Hansson
stats: Update stats for DMA port send
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2012-10-23
Andreas Hansson
dev: Remove zero-time loop in DMA timing send
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2012-10-23
Andreas Hansson
stats: Update t1000 stats to match recent changes
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2012-10-15
Andreas Hansson
Mem: Fix incorrect logic in bus blocksize check
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2012-10-15
Andreas Hansson
Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15
Andreas Hansson
Mem: Separate the host and guest views of memory backing...
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2012-10-15
Andreas Hansson
Checkpoint: Make system serialize call children
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2012-10-15
Andreas Hansson
Mem: Use deque instead of list for bus retries
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2012-10-15
Andreas Hansson
Fix: Address a few minor issues identified by cppcheck
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2012-10-15
Andreas Hansson
Stats: Update stats for cache timings in cycles
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2012-10-15
Andreas Hansson
Mem: Use cycles to express cache-related latencies
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2012-10-15
Andreas Hansson
Stats: Update memtest stats after setting clock
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2012-10-15
Andreas Hansson
Configs: Set the memtest clock to a reasonable value
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2012-10-15
Andreas Hansson
Stats: Update stats for new default L1-to-L2 bus clock...
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2012-10-15
Andreas Hansson
Regression: Use CPU clock and 32-byte width for L1...
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2012-10-15
Andreas Hansson
Stats: Update stats for use of two-level builder
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2012-10-15
Andreas Hansson
Regression: Use addTwoLevelCacheHierarchy in configs
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2012-10-15
Andreas Hansson
Clock: Inherit the clock from parent by default
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2012-10-15
Andreas Hansson
Param: Fix proxy traversal to support chained proxies
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2012-10-15
Andreas Hansson
Mem: Use range operations in bus in preparation for...
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2012-10-11
Andreas Hansson
Mem: Determine bus block size during initialisation
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2012-10-11
Andreas Hansson
Doxygen: Update the version of the Doxyfile
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2012-09-27
Andreas Hansson
Configs: Fix memtest cache latency to match new parameters
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2012-09-27
Andreas Hansson
Configs: Fix memtest.py by moving the system port
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2012-09-24
Andreas Hansson
Stats: Update stats for twosys-tsunami after setting...
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2012-09-24
Andreas Hansson
Regression: Set the clock for twosys-tsunami CPUs
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2012-09-21
Andreas Hansson
SimpleDRAM: A basic SimpleDRAM regression
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2012-09-21
Andreas Hansson
DRAM: Introduce SimpleDRAM to capture a high-level...
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator regression
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2012-09-21
Andreas Hansson
TrafficGen: Add a basic traffic generator
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2012-09-21
Andreas Hansson
Mem: Tidy up bus member variables types
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2012-09-21
Andreas Hansson
Scons: Verbose messages when dependencies are not installed
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2012-09-19
Andreas Hansson
Mem: Remove the file parameter from AbstractMemory
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2012-09-19
Andreas Hansson
AddrRange: Transition from Range<T> to AddrRange
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2012-09-19
Andreas Hansson
AddrRange: Simplify Range by removing stream input...
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2012-09-19
Andreas Hansson
AddrRange: Remove unused range_multimap
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2012-09-19
Andreas Hansson
AddrRange: Simplify AddrRange params Python hierarchy
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2012-09-18
Andreas Hansson
Stats: Update stats to reflect SimpleMemory bandwidth
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2012-09-18
Andreas Hansson
Mem: Add a maximum bandwidth to SimpleMemory
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2012-09-14
Andreas Hansson
gcc: Enable Link-Time Optimization for gcc >= 4.6
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2012-09-14
Andreas Hansson
scons: Add a target for google-perftools profiling
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2012-09-14
Andreas Hansson
scons: Restructure ccflags and ldflags
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2012-09-14
Andreas Hansson
scons: Use c++0x with gcc >= 4.4 instead of 4.6
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2012-09-13
Andreas Hansson
Stats: Remove the reference stats that are no longer...
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2012-09-11
Andreas Hansson
clang: Fix issues identified by the clang static analyzer
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2012-09-11
Andreas Hansson
Checkpoint: Pass maxtick to avoid undefined variable
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