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genlib.io: import TSTriple from Migen.
2018-12-14 whitequarkgenlib.io: import TSTriple from Migen.
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2018-12-14 whitequarkfhdl.ast: fix Switch with constant test.
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2018-12-14 whitequarkcompat: add genlib.cdc.MultiReg shim.
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2018-12-14 whitequarkcompat.fhdl.module: update deprecation messages.
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2018-12-14 whitequarkback.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 whitequarkback.pysim: better naming. NFC.
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2018-12-14 whitequarkTravis: install pyvcd.
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2018-12-14 whitequarkback.pysim: implement most operators and add tests.
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2018-12-14 whitequarkback.pysim: close .vcd/.gtkw files on context manager...
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2018-12-14 whitequarkback.pysim: show more legible names for processes in...
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2018-12-14 whitequarkback.pysim: throw exceptions back at processes.
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2018-12-14 whitequarkback.pysim: add gtkw traces even more robustly.
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2018-12-14 whitequarkback.pysim: accept (and evaluate) generator functions.
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2018-12-14 whitequarkback.pysim: skip VCD signal population if VCD is not...
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2018-12-14 whitequarkback.pysim: allow processes to evaluate expressions.
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2018-12-14 whitequarkfhdl.ir: oops, we defined DomainError twice.
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2018-12-14 whitequarkback.pysim: more general clean-up.
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2018-12-14 whitequarkback.pysim: general clean-up.
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2018-12-14 whitequarkback.pysim: accept any valid assignments from processes.
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2018-12-14 whitequarkback.pysim: robustly retrieve vcd names for clk/rst...
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2018-12-14 whitequarkfhdl.xfrm: implement DomainLowerer.
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2018-12-14 whitequarkback.pysim: undriven comb signals should return to...
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2018-12-14 whitequarkast, back.pysim: allow specifying user-defined decoders...
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2018-12-14 whitequarkback.pysim: fix completely broken codegen for Switch.
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2018-12-14 whitequarkback.pysim: raise an exception if delta cycles blow...
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2018-12-14 whitequarkback.pysim: if requested, write a gtkw file with a...
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2018-12-14 whitequarkback.pysim: explain how delta cycles work.
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2018-12-14 whitequarkback.pysim: delay clock processes by one half period.
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2018-12-14 whitequarkback.pysim: implement "sync processes", like migen...
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2018-12-14 whitequarkback.pysim: allow suspending processes until a tick...
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2018-12-14 whitequarkback.pysim: use bare ints for signal values (-5% runtime).
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2018-12-14 whitequarksetup: add missing import.
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2018-12-13 whitequarkback.pysim: collect handlers before running (-5% runtime).
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2018-12-13 whitequarkback.pysim: allow multiple registered handlers per...
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2018-12-13 whitequarkback.pysim: fix handling of process termination.
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2018-12-13 whitequarkback.pysim: new simulator backend (WIP).
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2018-12-13 whitequarkfhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 whitequarkfhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 whitequarkback.verilog: remove debug code.
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2018-12-13 whitequarkfhdl.ir: record port direction explicitly.
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2018-12-13 whitequarkcompat.genlib.fsm: import/wrap Migen code.
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2018-12-13 whitequarkfhdl.ir: a subfragment's input that we don't drive...
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2018-12-13 whitequarkfhdl, back: trace and emit source locations of values.
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2018-12-13 whitequarkback.rtlil: never give subfragment cells names starting...
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2018-12-13 whitequarkfhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 whitequarkfhdl.ir: implement clock domain propagation.
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2018-12-13 whitequarkfhdl.ir: remove iter_domains().
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2018-12-13 whitequarkfhdl: cd_name→domain.
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2018-12-13 whitequarkfhdl.cd: add tests.
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2018-12-13 whitequarkfhdl.xfrm: implement DomainRenamer.
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2018-12-13 whitequarkfhdl.xfrm: add test for ControlInserter with subfragments.
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2018-12-13 whitequarkfhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 whitequarkfhdl.ir: add tests for port propagation.
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2018-12-13 whitequarkSet up Travis CI.
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2018-12-13 whitequarkAdd LICENSE.
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2018-12-13 whitequarksetup: check Python version.
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2018-12-13 whitequarkfhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 whitequarkfhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 whitequarkfhdl.dsl: add tests for submodules.
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2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level...
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2018-12-13 whitequarkfhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 whitequarkfhdl.ast: fix Switch._?hs_signals() for switch without...
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2018-12-13 whitequarkback.verilog: detect undriven public wires using Yosys.
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2018-12-13 whitequarkback.rtlil: fix swapped operands in sync assign.
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2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion.
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2018-12-13 whitequarkback.rtlil: explicitly set the top module.
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2018-12-13 whitequarkfhdl.ir: explain how port enumeration works.
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2018-12-13 whitequarkback.rtlil: explain how RTLIL conversion works.
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2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear...
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2018-12-13 whitequarkback.rtlil: give clocks and resets nicer names.
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2018-12-13 whitequarkcompat.fhdl.module: implement finalization.
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2018-12-13 whitequarkback.rtlil: match shape of $mux ports A/B/Y.
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2018-12-13 whitequarktracer: add support for Python 3.7.
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2018-12-13 whitequarkfhdl.ast: bits_sign→shape.
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2018-12-13 whitequarkfhdl.ast: add tests for most logic.
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2018-12-13 whitequarkMeasure test coverage.
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2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code...
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2018-12-12 whitequarkcompat.fhdl.bitcontainer: import/wrap Migen code.
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2018-12-12 whitequarkfhdl.ast.Signal: implement .like().
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2018-12-12 whitequarkfhdl.ir: fix port threading code.
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2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 whitequarkfhdl.ast.Signal: fix typo.
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2018-12-12 whitequarkfhdl.ast.Signal: implement attrs field.
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2018-12-12 whitequarkgenlib.cdc.MultiReg: self.regs should be a private...
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2018-12-12 whitequarkfhdl.ast.Signal: implement width derivation from min...
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2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen.
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2018-12-12 whitequarkfhdl.ast.Signal: implement reset_less signals.
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2018-12-12 whitequarkfhdl.ast.Signal: assign an internal name if tracer...
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2018-12-12 whitequarkfhdl.dsl: allow f.sync["dom"] as a synonym of f.sync...
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2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInserter.
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2018-12-12 whitequarkInitial commit.
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