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Merge pull request #211 from shenki/spi-constraint
2020-06-17 Paul MackerrasMerge pull request #207 from ozbenh/misc
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2020-06-16 Paul Mackerrasfpga: Add a xilinx_specific fileset to microwatt.core
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-16 Paul MackerrasMake LOG_LENGTH configurable per FPGA variant
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasexecute1: Reduce width of the result mux to help timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrascore: Implement a simple branch predictor
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-15 Paul Mackerrasdecode1: Improve timing for slow SPR decode path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-14 Paul Mackerrasdecode1: Add a stash buffer to the output
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce back-to-back store latency from 3 cycles...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmmu: Take an extra cycle to do TLB invalidations
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdcache: Reduce latencies and improve timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasdecode: Work out ispr1/ispr2 in parallel with decode...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Reduce busy cycles
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasloadstore1: Complete mfspr/mtspr a cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Use a busy signal rather than a stall
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasicache: Improve latencies when reloading cache lines
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Use DSP48 slices for multiplication on Xilinx...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasmultiply: Move selection of result bits into execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Double the dcache and icache sizes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul MackerrasAdd core logging
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasscripts/mw_debug: Make progress counts display on one...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrastests/xics: Fix assumption that interrupts happen immediately
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul Mackerrasregister_file: Report value being written before asserting...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-13 Paul MackerrasMerge pull request #205 from ozbenh/timing
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2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
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2020-06-12 Paul MackerrasMerge pull request #198 from ozbenh/litedram
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2020-06-10 Paul MackerrasMerge pull request #194 from ozbenh/misc
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2020-06-05 Paul MackerrasMerge pull request #182 from mikey/travis
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2020-06-05 Paul Mackerrasdecode2: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul Mackerrasdecode1: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul Mackerrasdecode1: Make ld/std and lwa not be single-issue
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul MackerrasMerge pull request #191 from ozbenh/litedram
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2020-06-05 Paul Mackerrascore: Do addpcis using the main adder (#189)
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-06-05 Paul MackerrasMerge pull request #183 from shawnanastasio/addpcis
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2020-06-04 Paul MackerrasMerge pull request #185 from ozbenh/misc
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2020-06-03 Paul MackerrasMerge pull request #168 from shenki/flash-arty
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2020-05-15 Paul Mackerrasdcache: Fix bug in store hit after dcbz case
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-14 Paul Mackerrassoc: Work around compile error with ghdl 0.37-dev
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-14 Paul MackerrasMerge branch 'mmu'
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement reading of the process table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/mmu: Add a test of PTE refetching on permission...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/mmu: Add a test for dcbz with translation on
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement slbia as a dTLB/iTLB flush
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasDecode tlbiel as tlbie
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests/privileged: Update for instruction translation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests: mmu: Add tests for instruction translation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Do radix page table walks on iTLB misses
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd TLB to icache
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests: Add a test for the MMU radix page table walks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Remove software-loaded dTLB mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Refetch PTE on access fault
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement data segment interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement radix page table machinery
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd framework for implementing an MMU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement access permission checks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement data storage interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdcache: Implement data TLB
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasPass mtspr/mfspr to MMU-related SPRs down to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasmw_debug: Add support for reading GSPRs and writing...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdebug: Provide a way to examine GPRs, fast SPRs and MSR
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImprove architectural compliance of mfspr and mtspr
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdecode1: Implement eieio as a nop
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement the extswsli instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerrasexecute1: Fix interrupt delivery during slow instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerraswishbone_debug_master: Fix address auto-increment for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul MackerrasMerge remote-tracking branch 'remotes/origin/master'
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2020-05-06 Paul Mackerrasdcache: Don't assert on dcbz cache hit
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasChange the default cross compiler prefix to powerpc64le...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasMakefile: fix typo
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul Mackerrastests: Add a test for privileged instruction interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasdcache: Implement the dcbz instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul MackerrasPlumb insn_type through to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Generate privileged instruction interrupts...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Improve architecture compliance of MSR and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-22 Paul Mackerrasexecute1: Don't execute ld/st instruction when taking...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasDecode attn in the major opcode decode table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasDecode sc in the major opcode decode table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasRemove sim_config instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrasexecute1: Implement trap instructions properly
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasConsolidate trap variants under a single OP_TRAP
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrasexecute1: Simplify the interrupt logic a little
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasRename OP_MCRF to OP_CROP and trim insn_type_t
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrastests: Put an attn instruction at 0x700
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul MackerrasGive exceptions a separate path to writeback
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrastests: Update executables
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrastests: Adjust header inclusions and Makefile.test
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrashello_world: Use ldcix/stdcix to access UART
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrashello_world: Adjust header inclusions and Makefile
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-30 Paul Mackerrasloadstore1: Add support for cache-inhibited load and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-29 Paul Mackerrasloadstore1: Move load data formatting from writeback...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-28 Paul Mackerrasloadstore1: Move logic from dcache to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-05 Paul Mackerrasdcache: Remove LOAD_UPDATE2 state
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-04 Paul Mackerrasdcache: Trim one cycle from the load hit path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-27 Paul Mackerrasdcache: Implement load-reserve and store-conditional...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-26 Paul Mackerrasdcache: Add support for unaligned loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-21 Paul Mackerrasdcache: Fix obscure bug and minor cleanups
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-19 Paul MackerrasRemove single-issue constraint for most loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-05 Paul Mackerrasexecute1: Use truth table embedded in instruction for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasdecode1: Mark subfic as pipelined
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrascountzero: Add a register to help make timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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