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2020-12-01	Kito Cheng	RISC-V: Drop some commited accidentally code.	commit \| commitdiff \| tree
2020-11-30	Kito Cheng	RISC-V: Always define MULTILIB_DEFAULTS	commit \| commitdiff \| tree
2020-11-30	Kito Cheng	Fix print_multilib_info when default arguments appear...	commit \| commitdiff \| tree
2020-11-18	Kito Cheng	RISC-V: Support version controling for ISA standard...	commit \| commitdiff \| tree
2020-11-18	Kito Cheng	RISC-V: Support zicsr and zifencei extension for -march.	commit \| commitdiff \| tree
2020-11-18	Kito Cheng	RISC-V: Handle implied extension in canonical ordering.	commit \| commitdiff \| tree
2020-11-06	Kito Cheng	RISC-V: Mark non-export symbol static and const in...	commit \| commitdiff \| tree
2020-11-06	Kito Cheng	PR target/96307: Fix KASAN option checking.	commit \| commitdiff \| tree
2020-11-02	Kito Cheng	RISC-V: Check multiletter extension has more than 1...	commit \| commitdiff \| tree
2020-11-02	Kito Cheng	RISC-V: Add configure option: --with-multilib-generator...	commit \| commitdiff \| tree
2020-10-27	Kito Cheng	RISC-V: Refine riscv_parse_arch_string	commit \| commitdiff \| tree
2020-10-22	Kito Cheng	RISC-V: Extend syntax for the multilib-generator	commit \| commitdiff \| tree
2020-10-16	Kito Cheng	RISC-V: Handle implied extension in multilib-generator	commit \| commitdiff \| tree
2020-10-15	Kito Cheng	RISC-V: Add support for -mcpu option.	commit \| commitdiff \| tree
2020-10-14	Kito Cheng	PR target/96759 - Handle global variable assignment...	commit \| commitdiff \| tree
2020-09-29	Kito Cheng	RISC-V: Define __riscv_cmodel_medany for PIC mode.	commit \| commitdiff \| tree
2020-07-30	Cooper Qu	RISC-V: Add support for TLS stack protector canary...	commit \| commitdiff \| tree
2020-07-23	Kito Cheng	PR target/96260 - KASAN should work even back-end not...	commit \| commitdiff \| tree
2020-07-21	Kito Cheng	testsuite: Add signal checking for signal related testcase...	commit \| commitdiff \| tree
2020-07-09	Kito Cheng	RISC-V: Implement __builtin_thread_pointer	commit \| commitdiff \| tree
2020-07-09	Kito Cheng	RISC-V: Disable remove unneeded save-restore call optimizati...	commit \| commitdiff \| tree
2020-07-02	Kito Cheng	RISC-V: Handle multi-letter extension for multilib...	commit \| commitdiff \| tree
2020-07-01	Kito Cheng	RISC-V: Preserve arch version info during normalizing...	commit \| commitdiff \| tree
2020-06-22	Kito Cheng	RISC-V: Normalize arch string in driver time	commit \| commitdiff \| tree
2020-06-22	Kito Cheng	RISC-V: Fix compilation failed for frflags builtin...	commit \| commitdiff \| tree
2020-06-16	Kito Cheng	RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]	commit \| commitdiff \| tree
2020-06-15	Kito Cheng	RISC-V: Suppress warning for signed and unsigned integer...	commit \| commitdiff \| tree
2020-06-11	Kito Cheng	RISC-V: Unify the output asm pattern between gpr_save...	commit \| commitdiff \| tree
2020-06-11	Kito Cheng	RISC-V: Describe correct USEs for gpr_save pattern...	commit \| commitdiff \| tree
2020-06-02	Kito Cheng	testsuite: Disable colorization for ubsan test	commit \| commitdiff \| tree
2020-05-20	Kito Cheng	Fix alignment for local variable [PR90811]	commit \| commitdiff \| tree
2020-05-19	Kito Cheng	RISC-V: Handle implied extension for -march parser.	commit \| commitdiff \| tree
2020-05-19	Kito Cheng	RISC-V: Update march parser	commit \| commitdiff \| tree
2020-05-11	Kito Cheng	testsuite: Require gnu-tm support for pr94856.C	commit \| commitdiff \| tree
2020-03-11	Kito Cheng	RISC-V: Fix testsuite regression due to recent IRA... Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2020-03-06	Kito Cheng	RISC-V: Fix testsuite regression due to recent IRA...	commit \| commitdiff \| tree
2020-03-06	Kito Cheng	re PR tree-optimization/90883 (Generated code is worse...	commit \| commitdiff \| tree
2020-03-04	Kito Cheng	PR target/93995 ICE in patch_jump_insn, at cfgrtl.c...	commit \| commitdiff \| tree
2020-02-24	Kito Cheng	RISC-V: Adjust floating point code gen for LTGT compare Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2020-02-19	Kito Cheng	RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2020-01-21	Kito Cheng	RISC-V: Disallow regrenme if the TO register never...	commit \| commitdiff \| tree

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