| 2017-10-10 |
Clifford Wolf | Rewrite ABC output to include proper net names in timing...
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commit | commitdiff | tree |
| 2017-10-10 |
Clifford Wolf | Add timing constraints to osu035 example
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commit | commitdiff | tree |
| 2017-10-10 |
Clifford Wolf | Remove some dead code
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commit | commitdiff | tree |
| 2017-10-10 |
Clifford Wolf | Allow $past, $stable, $rose, $fell in $global_clock...
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commit | commitdiff | tree |
| 2017-10-07 |
Clifford Wolf | Add $shiftx support to verilog front-end
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commit | commitdiff | tree |
| 2017-10-06 |
Clifford Wolf | Update ABC to hg rev 0fc1803a77c0
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commit | commitdiff | tree |
| 2017-10-05 |
Larry Doolittle | Clean whitespace and permissions in techlibs/intel
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commit | commitdiff | tree |
| 2017-10-05 |
Clifford Wolf | Improve handling of Verific errors
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commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Improve Verific error handling, check VHDL static asserts
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commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Add blackbox command
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commit | commitdiff | tree |
| 2017-10-04 |
Clifford Wolf | Fix nasty bug in Verific bindings
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commit | commitdiff | tree |
| 2017-10-03 |
Clifford Wolf | Merge branch 'pr_ast_const_funcs' of https://github...
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commit | commitdiff | tree |
| 2017-10-03 |
Clifford Wolf | Merge branch 'fix_shift_reduce_conflict' of https:...
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commit | commitdiff | tree |
| 2017-10-03 |
Clifford Wolf | Merge branch 'dh73-master'
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commit | commitdiff | tree |
| 2017-10-03 |
Clifford Wolf | Rename "write_verilog -nobasenradix" to "write_verilog...
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commit | commitdiff | tree |
| 2017-09-29 |
Clifford Wolf | Add first draft of eASIC back-end
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commit | commitdiff | tree |
| 2017-09-29 |
Clifford Wolf | Fix synth_ice40 doc regarding -top default
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commit | commitdiff | tree |
| 2017-09-29 |
Clifford Wolf | Allow $size and $bits in verilog mode, actually check...
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commit | commitdiff | tree |
| 2017-09-27 |
Clifford Wolf | Increase maximum LUT size in blifparse to 12 bits
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commit | commitdiff | tree |
| 2017-09-26 |
Clifford Wolf | Parse reals as string in JSON front-end
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commit | commitdiff | tree |
| 2017-09-26 |
Clifford Wolf | Merge branch 'vlogpp-inc-fixes'
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commit | commitdiff | tree |
| 2017-09-26 |
Clifford Wolf | Minor coding style fix
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commit | commitdiff | tree |
| 2017-09-26 |
Clifford Wolf | Merge branch 'master' of https://github.com/combinatorylogic...
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commit | commitdiff | tree |
| 2017-09-25 |
Clifford Wolf | Fix ignoring of simulation timings so that invalid...
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commit | commitdiff | tree |
| 2017-09-15 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys
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commit | commitdiff | tree |
| 2017-09-15 |
Clifford Wolf | Update ABC to hg rev cd6984ee82d4
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commit | commitdiff | tree |
| 2017-09-09 |
Clifford Wolf | Add src attribute to extra cells generated by proc_dlatch
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commit | commitdiff | tree |
| 2017-09-09 |
Clifford Wolf | Add src arguments to all cell creator helper functions
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commit | commitdiff | tree |
| 2017-09-02 |
Clifford Wolf | Further improve extract_fa (but still buggy)
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commit | commitdiff | tree |
| 2017-09-01 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys
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commit | commitdiff | tree |
| 2017-09-01 |
Clifford Wolf | Merge branch 'ChipScan-master'
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commit | commitdiff | tree |
| 2017-09-01 |
Clifford Wolf | Update more stuff to use get_src_attribute() and set_src_att...
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commit | commitdiff | tree |
| 2017-08-30 |
Clifford Wolf | Add {get,set}_src_attribute() methods on RTLIL::AttrObject
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commit | commitdiff | tree |
| 2017-08-28 |
Clifford Wolf | Merge branch 'azonenberg-recover-reduce'
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commit | commitdiff | tree |
| 2017-08-28 |
Clifford Wolf | Rename recover_reduce to extract_reduce, fix args handling
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commit | commitdiff | tree |
| 2017-08-28 |
Clifford Wolf | Merge branch 'recover-reduce' of https://github.com...
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commit | commitdiff | tree |
| 2017-08-28 |
Clifford Wolf | Further improve extract_fa pass
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Don't track , ... contradictions through x/z-bits
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Add removing of redundant pairs of bits in ==, ===...
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Merge branch 'extract_fa'
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Further improve extract_fa (seems to be fully functional...
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Rename "adders" to "extract_fa"
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commit | commitdiff | tree |
| 2017-08-25 |
Clifford Wolf | Fix bug in write_smt2 (export logic driving hierarchical...
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commit | commitdiff | tree |
| 2017-08-23 |
Clifford Wolf | Towards more generic "adder" function extractor
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commit | commitdiff | tree |
| 2017-08-22 |
Clifford Wolf | Add experimental adders pass
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commit | commitdiff | tree |
| 2017-08-22 |
Clifford Wolf | Add hashlib support for hashing of pools
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commit | commitdiff | tree |
| 2017-08-22 |
Clifford Wolf | Add consteval support for $_ANDNOT_ and $_ORNOT_
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commit | commitdiff | tree |
| 2017-08-21 |
Clifford Wolf | Remove some dead code from fsm_map
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commit | commitdiff | tree |
| 2017-08-20 |
Clifford Wolf | Rename "singleton" pass to "uniquify"
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | More intuitive handling of "cd .." for singleton modules
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | Add "sim -zinit -rstlen"
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | Merge branch 'sim'
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | Add "sim" support for memories
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | Add Const methods is_fully_zero(), is_fully_def(),...
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commit | commitdiff | tree |
| 2017-08-18 |
Clifford Wolf | Add support for assert/assume/cover to "sim" command
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commit | commitdiff | tree |
| 2017-08-17 |
Clifford Wolf | Add writeback mode to "sim" command
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commit | commitdiff | tree |
| 2017-08-17 |
Clifford Wolf | Improve "sim" command
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commit | commitdiff | tree |
| 2017-08-16 |
Clifford Wolf | Add "sim" command skeleton
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commit | commitdiff | tree |
| 2017-08-15 |
Clifford Wolf | Merge branch 'azonenberg-rmports'
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commit | commitdiff | tree |
| 2017-08-15 |
Clifford Wolf | Mostly coding style related fixes in rmports pass
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commit | commitdiff | tree |
| 2017-08-15 |
Clifford Wolf | Merge branch 'rmports' of https://github.com/azonenberg...
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commit | commitdiff | tree |
| 2017-08-09 |
Clifford Wolf | Add support for set-reset cell variants to opt_rmdff
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commit | commitdiff | tree |
| 2017-08-09 |
Clifford Wolf | Auto-detect JSON front-end
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commit | commitdiff | tree |
| 2017-08-06 |
Clifford Wolf | Add handling of constant reset signals to opt_rmdff
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commit | commitdiff | tree |
| 2017-08-04 |
Clifford Wolf | Add "yosys-smtbmc --smtc-init --smtc-top --noinit"
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commit | commitdiff | tree |
| 2017-08-04 |
Clifford Wolf | Add "-undefined dynamic_lookup" to OSX "yosys-config...
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commit | commitdiff | tree |
| 2017-07-29 |
Clifford Wolf | Fix typo in "abc" pass help message
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Add merging of "past FFs" to verific importer
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Add consolidation of init attributes to opt_clean,...
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Add minimal support for PSL in VHDL via Verific
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Add simple VHDL+PSL example
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Improve Verific HDL language options
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commit | commitdiff | tree |
| 2017-07-28 |
Clifford Wolf | Fix handling of non-user-declared Verific netbus
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Improve Verific SVA importer
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Add counter.sv SVA test
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Add log_warning_noprefix() API, Use for Verific warnings...
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Add "verific -import -n" and "verific -import -nosva"
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Improve SVA tests, add Makefile and scripts
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Improve Verific SVA import: negedge and $past
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commit | commitdiff | tree |
| 2017-07-27 |
Clifford Wolf | Improve Verific SVA importer
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commit | commitdiff | tree |
| 2017-07-26 |
Clifford Wolf | Add "opt_expr -fine" feature to remove neutral bits...
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commit | commitdiff | tree |
| 2017-07-26 |
Clifford Wolf | Improve Verific bindings (mostly related to SVA)
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commit | commitdiff | tree |
| 2017-07-25 |
Clifford Wolf | Improve "help verific" message
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commit | commitdiff | tree |
| 2017-07-25 |
Clifford Wolf | Add "verific -extnets"
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commit | commitdiff | tree |
| 2017-07-25 |
Clifford Wolf | Add "using std::get" to yosys.h
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commit | commitdiff | tree |
| 2017-07-25 |
Clifford Wolf | Improve "verific -all" handling
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commit | commitdiff | tree |
| 2017-07-24 |
Clifford Wolf | Add "verific -import -d <dump_file"
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commit | commitdiff | tree |
| 2017-07-24 |
Clifford Wolf | Add "verific -import -flatten" and "verific -import -v"
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commit | commitdiff | tree |
| 2017-07-22 |
Clifford Wolf | Add more SVA test cases for future Verific work
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commit | commitdiff | tree |
| 2017-07-22 |
Clifford Wolf | Add "verific -import -k"
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commit | commitdiff | tree |
| 2017-07-22 |
Clifford Wolf | Add error for cell output ports that are connected...
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commit | commitdiff | tree |
| 2017-07-22 |
Clifford Wolf | Add some simple SVA test cases for future Verific work
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commit | commitdiff | tree |
| 2017-07-22 |
Clifford Wolf | Improve docs for verific bindings, add simply sby example
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commit | commitdiff | tree |
| 2017-07-21 |
Clifford Wolf | Fix handling of empty cell port assignments (i.e. ignore...
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commit | commitdiff | tree |
| 2017-07-21 |
Clifford Wolf | Fix "read_blif -wideports" handling of cells with wide...
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commit | commitdiff | tree |
| 2017-07-21 |
Clifford Wolf | Add a paragraph about pre-defined macros to read_verilog...
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commit | commitdiff | tree |
| 2017-07-21 |
Clifford Wolf | Add verilator support to testbenches generated by yosys...
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commit | commitdiff | tree |
| 2017-07-18 |
Clifford Wolf | Change intptr_t to uintptr_t in hashlib.h
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commit | commitdiff | tree |
| 2017-07-14 |
Clifford Wolf | Add $alu to list of supported cells for "stat -width"
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commit | commitdiff | tree |
| 2017-07-12 |
Clifford Wolf | Generate FSM-style testbenches in smtbmc
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commit | commitdiff | tree |
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