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verilog: fix $specify3 check
2018-12-07
whitequark
write_verilog: correctly map RTLIL `sync init`.
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2018-12-07
whitequark
equiv_opt: pass -D EQUIV when techmapping.
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tree
2018-12-07
whitequark
equiv_opt: new command, for verifying optimization...
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2018-12-07
whitequark
opt_lut: leave intact LUTs with cascade feeding module...
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tree
2018-12-07
whitequark
opt_lut: show original truth table for both cells.
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2018-12-07
whitequark
opt_lut: add -limit option, for debugging misoptimizations.
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tree
2018-12-06
whitequark
synth_ice40: split `map_gates` off `fine`.
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2018-12-05
whitequark
rename: add -src, for inferring names from source locations.
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2018-12-05
whitequark
lut2mux: handle 1-bit INIT constant in $lut cells.
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2018-12-05
whitequark
opt_lut: simplify type conversion. NFC.
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tree
2018-12-05
whitequark
synth_ice40: add -noabc option, to use built-in LUT...
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tree
2018-12-05
whitequark
gate2lut: new techlib, for converting Yosys gates to...
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2018-12-05
whitequark
Fix typo.
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2018-12-05
whitequark
opt_lut: add -dlogic, to avoid disturbing logic such...
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2018-12-05
whitequark
opt_lut: always prefer to eliminate 1-LUTs.
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2018-12-05
whitequark
opt_lut: collect and display statistics.
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2018-12-05
whitequark
opt_lut: refactor to use a worker. NFC.
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2018-12-05
whitequark
synth_ice40: add -relut option, to run ice40_unlut...
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2018-12-05
whitequark
opt_lut: new pass, to combine LUTs for tighter packing.
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2018-12-05
whitequark
Extract ice40_unlut pass from ice40_opt.
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2016-08-10
whitequark
synth_greenpak4: use attrmvcp to move LOC from wires...
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2016-07-12
whitequark
write_json: also write module attributes.
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2016-07-10
whitequark
greenpak4: add GP_COUNT{8,14}_ADV cells.
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