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2019-07-01	Sagar Ghuge	nir: Add optimization to use ROR/ROL instructions Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-07-01	Sagar Ghuge	nir: Add urol and uror opcodes Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-07-01	Sagar Ghuge	intel/compiler: Enable the emission of ROR/ROL instructions Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-06-25	Sagar Ghuge	glsl: Fix round64 conversion function Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-06-04	Sagar Ghuge	intel/compiler: Fix assertions in brw_alu3 Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-04-12	Sagar Ghuge	intel/fs: Remove unused condition from opt_algebraic... Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-08	Sagar Ghuge	iris: Track last VS URB entry size Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-08	Sagar Ghuge	iris: Refactor code to share 3DSTATE_URB_* packet Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-04	Sagar Ghuge	spirv: Allow [i/u]mulExtended to use new nir opcode Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-04	Sagar Ghuge	nir/algebraic: Optimize low 32 bit extraction Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-04	Sagar Ghuge	glsl: [u/i]mulExtended optimization for GLSL Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2019-03-04	Sagar Ghuge	nir/glsl: Add another way of doing lower_imul64 for... Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree
2018-12-18	Sagar Ghuge	nir: Add a new lowering option to lower 3D surfaces... Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>	commit \| commitdiff \| tree

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