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Merge pull request #852 from ucb-bar/firrtlfixes
2019-02-25 David Shahecp5: Compatibility with Migen AsyncResetSynchronizer
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-19 David Shahecp5: Add DDRDLLA
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-19 David Shahecp5: Add DELAYF/DELAYG blackboxes
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-13 David Shahecp5: Add ECLKSYNCB blackbox
Signed-off-by: David Shah <dave@ds0.me>
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2019-02-12 David Shahecp5: Full set of IO-related blackboxes
Signed-off-by: David Shah <dave@ds0.me>
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2019-02-07 David Shahfsm_opt: Fix runtime error for FSMs without a reset...
Signed-off-by: David Shah <dave@ds0.me>
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2019-02-06 David Shahecp5: Use abc -dress
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-06 David Shahabc: Improved recovered netnames, also preserve src...
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-06 David Shahice40: Use abc -dress in synth_ice40
Signed-off-by: David Shah <davey1576@gmail.com>
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2019-02-06 David Shahabc: Preserve naming through ABC using 'dress' command
Signed-off-by: David Shah <dave@ds0.me>
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2019-01-25 David ShahMerge pull request #796 from whitequark/proc_clean_typo
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2019-01-22 David Shahecp5: Support for flipflop initialisation
Signed-off-by: David Shah <dave@ds0.me>
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2019-01-21 David Shahecp5: Add LSRMODE to flipflops for PRLD support
Signed-off-by: David Shah <dave@ds0.me>
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2019-01-21 David Shahecp5: More blackboxes
Signed-off-by: David Shah <dave@ds0.me>
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2019-01-21 David Shahecp5: Increase threshold for ALU mapping
Signed-off-by: David Shah <dave@ds0.me>
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2018-12-18 David Shahmemory_dff: Fix typo when checking init value
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-12-12 David Shahdeminout: Consider $tribuf cells
Signed-off-by: David Shah <dave@ds0.me>
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2018-12-12 David Shahdeminout: Don't demote constant-driven inouts to inputs
Signed-off-by: David Shah <dave@ds0.me>
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2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut
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2018-12-06 David Shahabc: Preserve naming through ABC using 'dress' command
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-09 David Shahecp5: Add 'fake' DCU parameters
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells
Signed-off-by: David Shah <dave@ds0.me>
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2018-11-07 David Shahecp5: Adding some blackbox cells
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-22 David Shahecp5: Remove DSP parameters that don't work
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-21 David Shahecp5: Add DSP blackboxes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-10-19 David Shahecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 David Shahecp5: Add latch inference
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-19 David Shahmemory_bram: Reset make_outreg when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-16 David Shahecp5: Disable LSR inversion
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-12 David ShahBRAM improvements
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-10 David Shahecp5: Adding BRAM maps for all size options
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-10 David Shahecp5: First BRAM type maps successfully
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-10 David Shahecp5: Script for BRAM IO connections
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-09 David Shahecp5: Adding BRAM initialisation and config
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-05 David Shahecp5: Add blackbox for DP16KD
Signed-off-by: David Shah <dave@ds0.me>
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2018-10-01 David Shahecp5: Don't map ROMs to DRAM
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 David Shahecp5: Fixing miscellaneous sim model issues
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 David Shahecp5: Fixing 'X' issues with LUT simulation models
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-16 David Shahecp5: ECP5 synthesis fixes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-14 David Shahecp5: Adding synchronous set/reset support
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Add DRAM match rule
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Cells and mappings fixes
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Fixing arith_map
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Initial arith_map implementation
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Adding basic synth_ecp5 based on synth_ice40
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Adding DFF maps
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Adding DRAM map
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahecp5: Adding basic cells_sim and mapper for LUTs up...
Signed-off-by: David Shah <davey1576@gmail.com>
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2018-07-13 David Shahice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
Signed-off-by: David Shah <davey1576@gmail.com>
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2017-11-28 David ShahAdd remaining UltraPlus cells to ice40 techlib
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2017-11-18 David ShahRemove unnecessary keep attributes
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2017-11-17 David ShahMerge branch 'master' into up5k
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2017-11-16 David ShahAdd some UltraPlus cells to ice40 techlib
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