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ruby: banked cache array resource model
2012-07-09
Andreas Hansson
EventManager: Rename queue accessor and remove cast...
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2012-07-09
Andreas Hansson
Mem: Make members relating to range and size constant
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2012-07-09
Andreas Hansson
Port: Hide the queue implementation in SimpleTimingPort
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2012-07-09
Andreas Hansson
Stats: Updates due to bus changes
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2012-07-09
Andreas Hansson
Port: Align port names in C++ and Python
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2012-07-09
Andreas Hansson
Bus: Make the default bus width 8 bytes instead of 64
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2012-07-09
Andreas Hansson
Bus: Split the bus into separate request/response layers
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2012-07-09
Andreas Hansson
Bus: Add a notion of layers to the buses
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2012-07-09
Andreas Hansson
Bus: Replace tickNextIdle and inRetry with a state...
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2012-07-09
Andreas Hansson
Port: Make getAddrRanges const
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2012-07-09
Andreas Hansson
Port: Add getAddrRanges to master port (asking slave...
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2012-07-09
Andreas Hansson
Port: Add isSnooping to slave port (asking master port)
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2012-07-09
Andreas Hansson
Port: Move retry from port base class to Master/SlavePort
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2012-07-09
Andreas Hansson
Fix: Address a few benign memory leaks
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2012-07-02
Andreas Hansson
gcc: Fix warnings for gcc 4.7 and clang 3.1
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2012-06-20
Andreas Hansson
swig: Use SWIG from environment when determining version
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2012-06-18
Andreas Hansson
Build: Point to the appropriate tcmalloc package
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2012-06-08
Andreas Hansson
Timing CPU: Remove a redundant port pointer
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2012-06-08
Andreas Hansson
Power: Fix MaxMiscDestRegs which was set to zero
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2012-05-31
Andreas Hansson
Bus: Split the bus into a non-coherent and coherent bus
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2012-05-09
Andreas Hansson
Stats: Fix stats to match output after changeset 8800b05e1cb3
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2012-05-30
Andreas Hansson
gcc: Small fixes to compile with gcc 4.7
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2012-05-30
Andreas Hansson
Bus: Remove redundant packet parameter from isOccupied
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2012-05-30
Andreas Hansson
Bus: Turn the PortId into a transport function parameter
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2012-05-30
Andreas Hansson
Packet: Unify the use of PortID in packet and port
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2012-05-30
Andreas Hansson
Packet: Updated comments for src and dest fields
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2012-05-30
Andreas Hansson
Bridge: Split deferred request, response and sender...
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2012-05-24
Andreas Hansson
Cache: Remove dangling doWriteback declaration
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2012-05-23
Andreas Hansson
Packet: Cleaning up packet command and attribute
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2012-05-23
Andreas Hansson
Config: Use the attribute naming and include ports...
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2012-05-23
Andreas Hansson
DMA: Split the DMA device and IO device into seperate...
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2012-05-23
Andreas Hansson
MEM: Add a snooping DMA port subclass for table walker
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2012-05-23
Andreas Hansson
Config: Exit with fatal if a port is already connected
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2012-05-16
Andreas Hansson
Config: Fix a typo in the se.py script for setting...
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2012-05-09
Andreas Hansson
MEM: Add the communication monitor
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2012-05-08
Andreas Hansson
MEM: Do not forward uncacheable to bus snoopers
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2012-05-04
Andreas Hansson
Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
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2012-05-01
Andreas Hansson
MEM: Separate requests and responses for timing accesses
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2012-04-25
Andreas Hansson
MEM: Use base class Master/SlavePort pointers in the bus
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2012-04-25
Andreas Hansson
MEM: Add the PortId type and a corresponding id field...
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2012-04-25
Andreas Hansson
clang/gcc: Use STL hash function for int64_t and uint64_t
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2012-04-14
Andreas Hansson
Ruby: Use MasterPort base-class pointers where possible
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2012-04-14
Andreas Hansson
MEM: Remove the Broadcast destination from the packet
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2012-04-14
Andreas Hansson
MEM: Separate snoops and normal memory requests/responses
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2012-04-14
Andreas Hansson
Regression: Add ANSI colours to highlight test status
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2012-04-14
Andreas Hansson
clang/gcc: Fix compilation issues with clang 3.0 and...
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2012-04-12
Andreas Hansson
Stats: Update with use of std::map for ordered iteration...
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2012-04-12
Andreas Hansson
Ruby: Ensure order-dependent iteration uses an ordered map
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2012-04-06
Andreas Hansson
MEM: Enable multiple distributed generalized memories
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2012-04-05
Andreas Hansson
Ruby: Fix the example configurations option parsing
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2012-04-05
Andreas Hansson
Python: Make the All proxy traverse SimObject children...
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2012-04-03
Andreas Hansson
Atomic: Remove the physmem_port and access memory directly
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2012-03-30
Andreas Hansson
MEM: Remove legacy DRAM in preparation for memory updates
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2012-03-30
Andreas Hansson
Ruby: Remove the physMemPort and instead access memory...
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2012-03-30
Andreas Hansson
CPU: Unify initMemProxies across CPUs and simulation...
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2012-03-26
Andreas Hansson
range_map: Enable const find and iteration
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2012-03-26
Andreas Hansson
Power: Change bitfield name to avoid conflicts with...
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2012-03-23
Andreas Hansson
Ruby: Fix Set::print for 32-bit hosts
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2012-03-22
Andreas Hansson
MEM: Unify bus access methods and prepare for master...
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2012-03-22
Andreas Hansson
MEM: Split SimpleTimingPort into PacketQueue and ports
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2012-03-22
Andreas Hansson
Scons: Remove Werror=False in SConscript files
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2012-03-21
Andreas Hansson
Python: Fix a conditional expression that requires...
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2012-03-19
Andreas Hansson
gcc: Clean-up of non-C++0x compliant code, first steps
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2012-03-19
Andreas Hansson
clang: Fix recently introduced clang compilation errors
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2012-03-19
Andreas Hansson
scripts: Fix to ensure that port connection count is...
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2012-03-06
Andreas Hansson
Stats: Update stats for changeset 8868
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2012-03-02
Andreas Hansson
CPU: Check that the interrupt controller is created...
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2012-03-02
Andreas Hansson
Stats: Fix the realview regression stats after nvmem...
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2012-03-02
Andreas Hansson
Ruby: Rename RubyPort::sendTiming to avoid overriding...
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2012-02-29
Andreas Hansson
MEM: Make all the port proxy members const
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2012-02-29
Andreas Hansson
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
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2012-02-24
Andreas Hansson
MEM: Simplify cache ports preparing for master/slave...
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2012-02-24
Andreas Hansson
MEM: Prepare mport for master/slave split
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2012-02-24
Andreas Hansson
Ruby: Simplify tester ports by not using SimpleTimingPort
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2012-02-24
Andreas Hansson
MEM: Move all read/write blob functions from Port to...
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2012-02-24
Andreas Hansson
MEM: Make port proxies use references rather than pointers
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2012-02-24
Andreas Hansson
MEM: Move port creation to the memory object(s) construction
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2012-02-24
Andreas Hansson
CPU: Round-two unifying instr/data CPU ports across...
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2012-02-24
Andreas Hansson
MEM: Fatal when no port can be found for an address
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2012-02-14
Andreas Hansson
MEM: Fix residual bus ports and make them master/slave
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2012-02-14
Andreas Hansson
Script: Fix the scripts that use the num_cpus cache...
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2012-02-14
Andreas Hansson
MEM: Fix master/slave ports in Ruby and non-regression...
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2012-02-13
Andreas Hansson
MEM: Explicit ports and Python binding on CopyEngine
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2012-02-13
Andreas Hansson
MEM: Pass the ports from Python to C++ using the Swig...
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2012-02-13
Andreas Hansson
MEM: Introduce the master/slave port roles in the Python...
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2012-02-09
Andreas Hansson
MEM: Remove onRetryList from BusPort and rely on retryList
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2012-02-02
Andreas Hansson
Regression: Update the regress script after SE/FS merge
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2012-01-31
Andreas Hansson
MEM: Remove the otherPort from the cache ports
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2012-01-31
Andreas Hansson
Thread: Use inherited baseCpu rather than cpu in SimpleThread
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2012-01-30
Andreas Hansson
Ruby: Connect system port in Ruby network test
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2012-01-30
Andreas Hansson
MEM: Make the RubyPort physMemPort a PioPort instead...
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2012-01-30
Andreas Hansson
MEM: Clean-up of Functional/Virtual/TranslatingPort...
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2012-01-27
Andreas Hansson
ns_gige: Fix a missing curly brace in if-statement
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2012-01-25
Andreas Hansson
MEM: Fix fs.py by specifying the range size rather...
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2012-01-17
Andreas Hansson
MEM: Make the bus default port yet another port
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2012-01-17
Andreas Hansson
MEM: Removing the default port peer from Python ports
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2012-01-17
Andreas Hansson
MEM: Make the bus bridge unidirectional and fixed address...
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2012-01-17
Andreas Hansson
MEM: Separate queries for snooping and address ranges
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2012-01-17
Andreas Hansson
MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-17
Andreas Hansson
MEM: Remove the notion of the default port
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