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Added "equiv_struct -fwonly"
2016-01-08
Clifford Wolf
Added "equiv_struct -fwonly"
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2016-01-08
Clifford Wolf
Bugfixes in equiv_struct
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2016-01-08
Clifford Wolf
Added "submod -copy"
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2016-01-06
Clifford Wolf
Added "write_blif -cname" mode
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2016-01-06
Clifford Wolf
Added "equiv_struct -maxiter <N>"
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2016-01-06
Clifford Wolf
Added "equiv_add -try" mode
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2015-12-22
Clifford Wolf
Fixed "splitnets -ports" for hierarchical designs
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2015-12-22
Clifford Wolf
Re-run ice40_opt in "synth_ice40 -abc2"
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2015-12-22
Clifford Wolf
Improvements in ice40_opt
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2015-12-22
Clifford Wolf
Bugfix in ice40_ffinit
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2015-12-22
Clifford Wolf
Improved ice40_ffinit
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2015-12-22
Clifford Wolf
Run opt_const before check in default scripts
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2015-12-20
Clifford Wolf
Added %R select expression
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2015-12-20
Clifford Wolf
Various improvements in BLIF front-end
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2015-12-20
Clifford Wolf
Added yosys-smtbmc -S
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2015-12-15
Clifford Wolf
Merge pull request #110 from scanlime/master
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2015-12-08
Clifford Wolf
Added "synth_ice40 -abc2"
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-12-02
Clifford Wolf
Improved proc_mux performance for huge always blocks
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2015-12-02
Clifford Wolf
Added default values for hashlib at() methods
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2015-11-30
Clifford Wolf
Re-added SigMap::allbits()
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2015-11-30
Clifford Wolf
Added tests/simple/graphtest.v
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2015-11-29
Clifford Wolf
Fixed oom bug in ilang parser
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2015-11-27
Clifford Wolf
Fixed performance bug in ilang parser
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2015-11-26
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-11-26
Clifford Wolf
Removed dangling ';' in rtlil.h
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2015-11-26
Clifford Wolf
Added ice40_ffinit pass
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2015-11-24
Clifford Wolf
Added PRIM_DLATCHRS support to verific front-end
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2015-11-24
Clifford Wolf
Fixed WE/RE usage in iCE40 BRAM mapping
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2015-11-23
Clifford Wolf
Fixed handling of re-declarations of wires in tasks...
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2015-11-19
Clifford Wolf
Added torder command
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2015-11-16
Clifford Wolf
Fixed performance bug in Verific importer
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2015-11-12
Clifford Wolf
Changes for Verific 3.16_484_32_151112
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2015-11-12
Clifford Wolf
Link to vlsitechnology.org for liberty files
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2015-11-12
Clifford Wolf
More bugfixes in handling of parameters in tasks and...
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2015-11-11
Clifford Wolf
Fixed handling of parameters and localparams in functions
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2015-11-10
Clifford Wolf
Added "abc -g"
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2015-11-08
Clifford Wolf
Merge pull request #97 from zeldin/master
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2015-11-07
Clifford Wolf
Added "singleton" pass
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2015-11-06
Clifford Wolf
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
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2015-11-05
Clifford Wolf
Bugfix in mapping $tribuf to $_TBUF_
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2015-10-31
Clifford Wolf
Bugfix in memory_dff
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2015-10-31
Clifford Wolf
Improvements in wreduce
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2015-10-30
Clifford Wolf
Bugfix in Xilinx LUT mapping
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2015-10-28
Clifford Wolf
Improved SigMap performance
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2015-10-27
Clifford Wolf
Improvements in new SigMap
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2015-10-27
Clifford Wolf
Use mfp<> in equiv_mark
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2015-10-27
Clifford Wolf
Removed old SigMap implementation
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2015-10-27
Clifford Wolf
Added hashlib::mfp and new SigMap
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2015-10-25
Clifford Wolf
Improvements in equiv_struct
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2015-10-25
Clifford Wolf
Major refactoring of equiv_struct
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2015-10-25
Clifford Wolf
Import more std:: stuff into Yosys namespace
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2015-10-25
Clifford Wolf
Added "equiv_add -cell"
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2015-10-25
Clifford Wolf
equiv_struct now creates equiv_merged attributes
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2015-10-24
Clifford Wolf
Improvements in equiv_struct
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2015-10-24
Clifford Wolf
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit...
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2015-10-24
Clifford Wolf
improvement in "stat"
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2015-10-24
Clifford Wolf
Fixed driver conflict handling (various cmds)
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2015-10-24
Clifford Wolf
equiv_purge bugfix, using SigChunk in Yosys namespace
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2015-10-24
Clifford Wolf
Fixed handling of driver-driver conflicts in wreduce
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2015-10-23
Clifford Wolf
Added equiv_mark command
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2015-10-23
Clifford Wolf
Disabled "Skipping blackbox module" msg in show command
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2015-10-23
Clifford Wolf
Added support for ":" as comment symbol after ;-parsing
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2015-10-23
Clifford Wolf
Also merge $equiv cells in equiv_struct
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2015-10-23
Clifford Wolf
Improvements in equiv_struct
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2015-10-22
Clifford Wolf
Added equiv_purge
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2015-10-21
Clifford Wolf
Added equiv_struct command
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2015-10-21
Clifford Wolf
Improved inout handling in equiv_make
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2015-10-20
Clifford Wolf
Progress on cell help messages
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2015-10-17
Clifford Wolf
Progress on cell help messages
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2015-10-15
Clifford Wolf
Progress in yosys-smtbmc
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2015-10-15
Clifford Wolf
Fixed bug in verilog parser
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2015-10-15
Clifford Wolf
Improvements in yosys-smtbmc
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2015-10-15
Clifford Wolf
Bugfixes in handling of "keep" attribute on wires
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2015-10-14
Clifford Wolf
More "yosys-smtbmc -c" fixes
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2015-10-14
Clifford Wolf
Fixed yosys-smtbmc -c
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2015-10-14
Clifford Wolf
Added "prep" command
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2015-10-14
Clifford Wolf
Added more cell descriptions
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2015-10-14
Clifford Wolf
Added first help messages for cell types
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2015-10-13
Clifford Wolf
Added yosys-smtbmc copyright
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2015-10-13
Clifford Wolf
Improvements in yosys-smtbmc
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2015-10-13
Clifford Wolf
Added yosys-smtbmc
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2015-10-13
Clifford Wolf
Implemented smtbmc.py -i
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2015-10-13
Clifford Wolf
Added smtbmc.py
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2015-10-13
Clifford Wolf
Added write_smt2 -wires
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2015-10-13
Clifford Wolf
Added examples/ top-level directory
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2015-10-13
Clifford Wolf
SystemVerilog also has assume(), added implicit -D...
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2015-10-13
Clifford Wolf
Merge branch 'master' of https://github.com/rubund...
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2015-10-13
Clifford Wolf
Fixed "flatten" for unconnected inout ports
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2015-10-07
Clifford Wolf
Added support for "parameter" and "localparam" in global...
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2015-10-01
Clifford Wolf
Fixed complexity of assigning to vectors in constant...
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2015-09-30
Clifford Wolf
Fixed detection of unconditional $readmem[hb]
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2015-09-27
Clifford Wolf
Added edgetypes command
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2015-09-26
Clifford Wolf
Some cleanups in qwp
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2015-09-25
Clifford Wolf
Added "test_cell -noeval"
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2015-09-25
Clifford Wolf
Added wreduce $mul support and fixed signed $mul opt_const bug
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2015-09-25
Clifford Wolf
Bugfix in bram read-enable code
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2015-09-25
Clifford Wolf
Bugfixes in $readmem[hb]
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2015-09-25
Clifford Wolf
Bugfixes in writing of memories as Verilog
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2015-09-25
Clifford Wolf
Fixed segfault in AstNode::asReal
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