projects / mesa.git / search
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
i965: enable accumulator update in PS kernel too on sandybridge
2010-09-28 Zhenyu Wangi965: enable accumulator update in PS kernel too on...
commit | commitdiff | tree
2010-09-28 Zhenyu Wangi965: new state dump for sandybridge
 commit | commitdiff | tree
2010-09-28 Zhenyu Wangi965: disasm quarter and write enable instruction control...
commit | commitdiff | tree
2010-08-31 Zhenyu Wangi965: fix depth test on sandybridge
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2010-08-23 Zhenyu Wangi965: Add sandybridge D0 pci ids
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Add support for FB writes on Sandybridge.
 commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Set the destination horiz stride even for da16...
commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Set the maximum number of threads on Sandybridge.
 commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Add AccWrCtl support on Sandybridge.
 commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Mention the mlen and rlen for URB reads.
 commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Sandybridge doesn't have Compr4 mode, since it...
commit | commitdiff | tree
2010-08-20 Zhenyu Wangi965: Adjust disasm of subreg numbers to be in units...
commit | commitdiff | tree
2010-07-08 Zhenyu Wangi965: Add 'wait' instruction support
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2010-07-08 Zhenyu Wangi965: Add decode for Sandybridge DP write messages.
 commit | commitdiff | tree
2010-07-08 Zhenyu Wangi965: Add definitions for Sandybridge DP write/read...
commit | commitdiff | tree
2010-06-14 Zhenyu Wangi965: correct the gen6 line stipple enable define.
 commit | commitdiff | tree
2010-06-13 Zhenyu Wangi965: Use the new message header format for FF_SYNC...
commit | commitdiff | tree
2010-06-13 Zhenyu Wangi965: Add support for math instructions in the gen6 WM.
 commit | commitdiff | tree
2010-06-13 Zhenyu Wangi965: Set the correct WM GRF start reg on gen6.
 commit | commitdiff | tree
2010-04-21 Zhenyu Wangintel: Add Sandybridge mobile chipset id
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2010-04-21 Zhenyu Wangintel: Clean up chipset name and gen num for Ironlake
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2009-09-10 Zhenyu Wangintel: add B43 chipset support
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree
2009-09-09 Zhenyu Wangintel: add B43 chipset support
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
 commit | commitdiff | tree