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nexus: Fix arith_map CO signal.
2022-02-06 Marcelina Kościelnickanexus: Fix arith_map CO signal.
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2022-01-31 Marcelina Kościelnickaverilog backend: Emit a `wire` for ports as well.
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2022-01-30 Marcelina Kościelnickaopt_reduce: Add $bmux and $demux optimization patterns.
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2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
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2022-01-28 Marcelina Kościelnickaopt_dff: Don't mutate muxes while ModWalker is active.
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2022-01-28 Marcelina Kościelnickakernel/mem: Add read-first semantic emulation code.
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2022-01-27 Marcelina Kościelnickamanual: Fix a custom pass example.
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2022-01-27 Marcelina Kościelnickamemory_bram: Make use of new mem emulation functions...
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2022-01-27 Marcelina Kościelnickakernel/mem: Add functions to emulate read port enable...
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2021-12-20 Marcelina Kościelnickamemory_share: Fix SAT-based sharing for wide ports.
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2021-12-12 Marcelina KościelnickaAdd clean_zerowidth pass, use it for Verilog output.
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2021-12-12 Marcelina KościelnickaFix unused param warning with ENABLE_NDEBUG.
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2021-12-12 Marcelina Kościelnickartlil: Dump empty connections when whole module is...
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2021-12-08 Marcelina Kościelnickaopt_mem_priority: Fix non-ascii char in help message.
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2021-11-12 Marcelina Kościelnickashow: Fix wire bit indexing.
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2021-11-10 Marcelina Kościelnickaiopadmap: Fix ebmarassing typo
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2021-11-09 Marcelina Kościelnickaiopadmap: Add native support for negative-polarity...
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2021-11-02 Marcelina Kościelnickaflatten: Keep sigmap around between flatten_cell invocations.
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2021-10-27 Marcelina Kościelnickaecp5: Add support for mapping aldff.
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2021-10-27 Marcelina Kościelnickaproc_dff: Emit $aldff.
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2021-10-27 Marcelina Kościelnickadfflegalize: Add tests for aldff lowering.
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2021-10-27 Marcelina Kościelnickadfflegalize: Add tests targetting aldff.
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2021-10-27 Marcelina Kościelnickadfflegalize: Refactor, add aldff support.
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2021-10-21 Marcelina KościelnickaChange implicit conversions from bool to Sig* to explicit.
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2021-10-21 Marcelina Kościelnickaextract_reduce: Refactor and fix input signal construction.
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2021-10-08 Marcelina KościelnickaFix a regression from #3035.
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2021-10-07 Marcelina KościelnickaFfData: some refactoring.
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2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
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2021-10-02 Marcelina Kościelnickazinit: Refactor to use FfData.
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2021-10-02 Marcelina Kościelnickakernel/ff: Refactor FfData to enable FFs with async...
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2021-10-02 Marcelina KościelnickaAdd $aldff and $aldffe: flip-flops with async load.
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2021-10-02 Marcelina Kościelnickasimplemap: refactor to use FfData.
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2021-09-13 Marcelina Kościelnickaverilog: Squash flex-triggered warning.
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2021-09-10 Marcelina Kościelnickayosys-smtbmc: Fix reused loop variable.
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2021-08-22 Marcelina Kościelnickaopt_merge: Remove and reinsert init when connecting...
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2021-08-22 Marcelina Kościelnickaopt_clean: Make the init attribute follow the FF's Q.
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2021-08-16 Marcelina Kościelnickakernel/mem: Remove old parameter when upgrading $mem...
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2021-08-14 Marcelina Kościelnickaproc_prune: Make assign removal and promotion per-bit...
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2021-08-13 Marcelina KościelnickaAdd opt_mem_widen pass.
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2021-08-13 Marcelina Kościelnickamemory_share: Add -nosat and -nowiden options.
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2021-08-13 Marcelina Kościelnickamemory_dff: Recognize soft transparency logic.
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2021-08-13 Marcelina KościelnickaAdd new opt_mem_priority pass.
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2021-08-12 Marcelina Kościelnickamemory_share: Pass addresses through sigmap_xmux everywhere.
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2021-08-12 Marcelina Kościelnickalogger: Add -check-expected subcommand.
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2021-08-11 Marcelina Kościelnickatest/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
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2021-08-11 Marcelina Kościelnickamemory_dff: Recognize read ports with reset / initial...
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2021-08-11 Marcelina Kościelnickaproc_memwr: Use the v2 memwr cell.
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2021-08-11 Marcelina KościelnickaAdd v2 memory cells.
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2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
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2021-08-09 Marcelina KościelnickaRefactor common parts of SAT-using optimizations into...
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2021-08-07 Marcelina Kościelnickaopt_merge: Use FfInitVals.
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2021-08-06 Marcelina Kościelnickaverilog: Support tri/triand/trior wire types.
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2021-08-04 Marcelina Kościelnickamemory_share: Don't skip ports with EN wired to input...
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2021-08-03 Marcelina Kościelnickamemory_bram: Move init data swizzling before other...
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2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
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2021-08-01 Marcelina Kościelnickamemory_bram: Some refactoring
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2021-07-29 Marcelina Kościelnickaopt_lut: Allow more than one -dlogic per cell type.
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2021-07-28 Marcelina Kościelnickaverilog: Emit $meminit_v2 cell.
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2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
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2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
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2021-07-27 Marcelina Kościelnickaproc: Run opt_expr at the end
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2021-07-27 Marcelina Kościelnickaopt_expr: Propagate constants to port connections.
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2021-07-13 Marcelina Kościelnickakernel/mem: Add a coalesce_inits helper.
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2021-07-12 Marcelina Kościelnickakernel/mem: Use delayed removal for inits as well.
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2021-07-12 Marcelina Kościelnickakernel/mem: Add documentation for more helper functions.
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2021-07-12 Marcelina Kościelnickacxxrtl: Support memory writes in processes.
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2021-07-12 Marcelina Kościelnickacxxrtl: Add support for memory read port reset.
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2021-07-12 Marcelina Kościelnickacxxrtl: Add support for mem read port initial data.
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2021-07-12 Marcelina Kościelnickacxxrtl: Convert to Mem helpers.
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2021-07-12 Marcelina Kościelnickakernel/mem: Commit new values of attributes in emit.
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2021-07-12 Marcelina Kościelnickakernel/mem: Make the Mem helpers inherit from AttrObject.
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2021-07-11 Marcelina Kościelnickartlil: Make Process handling more uniform with Cell...
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2021-07-10 Marcelina Kościelnickaice40: Fix LUT input indices in opt_lut -dlogic (again).
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2021-06-14 Marcelina Kościelnickaverilog: Squash a memory leak.
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2021-06-11 Marcelina KościelnickaAdd regression test for #2824.
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2021-06-09 Marcelina Kościelnickaopt_expr: Fix mul/div/mod by POT patterns to support...
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2021-06-09 Marcelina Kościelnickaopt_expr: Optimize div/mod by const 1.
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2021-06-01 Marcelina Kościelnickakernel/mem: Recognize some deprecated memory port configs.
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2021-05-31 Marcelina Kościelnickamemory_map: Improve start_offset handling.
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2021-05-29 Marcelina Kościelnickamemory_share: Add read port merging.
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2021-05-28 Marcelina Kościelnickamemory_share: Improve sat-based port sharing.
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2021-05-27 Marcelina KościelnickaMake a few passes auto-call Mem::narrow instead of...
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2021-05-27 Marcelina Kościelnickabackends/verilog: Add support for memory read port...
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2021-05-27 Marcelina Kościelnickabackends/verilog: Add wide port support.
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2021-05-27 Marcelina Kościelnickamemory_share: Improve same-address merging, recognize...
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2021-05-27 Marcelina Kościelnickakernel/mem: Add helpers for write port widening.
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2021-05-26 Marcelina Kościelnickakernel/mem: Add sub_addr helpers.
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2021-05-26 Marcelina Kościelnickakernel/mem: Add prepare_wr_merge helper.
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2021-05-25 Marcelina Kościelnickabackends/verilog: Try to preserve mem write port priorities.
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2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix "no FF made" edge case.
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2021-05-25 Marcelina Kościelnickamemory_bram: Reuse extract_rdff helper for make_outreg.
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2021-05-25 Marcelina Kościelnickamem/extract_rdff: Add alternate transparency handling.
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2021-05-25 Marcelina Kościelnickaopt_mem: Add reset/init value support.
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2021-05-25 Marcelina Kościelnickakernel/mem: Add model support for read port init value...
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2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix wire naming and wide port support.
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2021-05-25 Marcelina Kościelnickamemory_bram: Respect write port priority.
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2021-05-25 Marcelina Kościelnickaopt_mem_feedback: Respect write port priority.
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2021-05-25 Marcelina Kościelnickakernel/mem: Add emulate_priority helper.
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2021-05-25 Marcelina KościelnickaAdd memory_narrow pass.
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2021-05-25 Marcelina Kościelnickamemory_share: Add wide port support.
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