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Added log_dump() support for IdStrings
2015-06-08
Clifford Wolf
Added log_dump() support for IdStrings
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2015-06-08
Clifford Wolf
Fixed handling of parameters with reversed range
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2015-05-31
Clifford Wolf
Added opt_share -share_all
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2015-05-31
Clifford Wolf
Added iCE40 PLL cells
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2015-05-31
Clifford Wolf
Added liberty dont_use support to dfflibmap
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2015-05-29
Clifford Wolf
Fixed signedness of genvar expressions
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2015-05-26
Clifford Wolf
Added output args to synth_ice40
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2015-05-24
Clifford Wolf
Improvements in BLIF front-end
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2015-05-23
Clifford Wolf
improved ice40 SB_IO sim model
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2015-05-23
Clifford Wolf
Improved "flatten" handlings of inout ports
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2015-05-23
Clifford Wolf
Added simple $dlatch support to opt_rmdff
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2015-05-23
Clifford Wolf
Added ice40 SB_IO sim model
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2015-05-22
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-05-22
Clifford Wolf
preserve used $-wires with init attribute in opt_clean
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2015-05-20
Clifford Wolf
Some fixes for $mem in verilog back-end
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2015-05-18
Clifford Wolf
bugfix in blif front-end
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2015-05-17
Clifford Wolf
added vloghtb test_febe.sh
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2015-05-17
Clifford Wolf
Improved .latch support in BLIF front-end
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2015-05-17
Clifford Wolf
Added read_blif command
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2015-05-17
Clifford Wolf
Generalized blifparse API
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2015-05-17
Clifford Wolf
abc/blifparse files reorganization
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2015-05-17
Clifford Wolf
Verific build fixes
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2015-05-13
Clifford Wolf
Added .barbuf support to abc BLIF parser
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2015-05-11
Clifford Wolf
changed file() to open() in python scripts
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2015-05-11
Clifford Wolf
Merge pull request #63 from wluker/verilog-backend-mem
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2015-05-10
Clifford Wolf
Disabled broken $mem support in verilog backend
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2015-05-10
Clifford Wolf
Merge pull request #62 from wluker/verilog-backend-mem
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2015-04-29
Clifford Wolf
Fixed memory_unpack for initialized memories
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2015-04-29
Clifford Wolf
Preserve important attributes in splitnets
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2015-04-29
Clifford Wolf
Added $eq/$neq -> $logic_not/$reduce_bool optimization
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2015-04-27
Clifford Wolf
ice40_opt bugfix
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2015-04-27
Clifford Wolf
iCE40: SB_CARRY const fold -> unmap SB_LUT
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2015-04-27
Clifford Wolf
Added simplemap $lut support
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2015-04-27
Clifford Wolf
Added iCE40 const folding support for SB_CARRY
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2015-04-26
Clifford Wolf
Initialization support for all iCE40 bram modes
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2015-04-25
Clifford Wolf
initialized iCE40 brams (mode 0)
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2015-04-25
Clifford Wolf
improved iCE40 SB_RAM40_4K simulation model
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2015-04-25
Clifford Wolf
Updated ABC to hg rev 779de2de1481
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2015-04-25
Clifford Wolf
More iCE40 bram improvements
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2015-04-24
Clifford Wolf
Improved attributes API and handling of "src" attributes
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2015-04-24
Clifford Wolf
iCE40 bram progress
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2015-04-24
Clifford Wolf
iCE40 bram tests and fixes
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2015-04-23
Clifford Wolf
Added ice40 bram support
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2015-04-22
Clifford Wolf
Fixed memory_share for unconditional write with part...
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2015-04-19
Clifford Wolf
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
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2015-04-19
Clifford Wolf
Verilog front-end: define `BLACKBOX in -lib mode
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2015-04-18
Clifford Wolf
added sync reset to ice40 test_ffs.sh
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2015-04-18
Clifford Wolf
Added ice40 test_arith
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2015-04-18
Clifford Wolf
Added ice40 SB_CARRY support
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2015-04-18
Clifford Wolf
don't consider blackbox modules in "sat" command
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2015-04-18
Clifford Wolf
Improved handling of init values in opt_rmdff
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2015-04-17
Clifford Wolf
Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
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2015-04-17
Clifford Wolf
Added mapping of synchronous set/reset to iCE40 flow
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2015-04-16
Clifford Wolf
Improved "maccmap" help message
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2015-04-16
Clifford Wolf
A "#" does start a comment, not a label.
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2015-04-16
Clifford Wolf
Changed ice40 ICESTORM_CARRYCONST port name
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2015-04-16
Clifford Wolf
Fixed "dff2dffe -direct-match"
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2015-04-16
Clifford Wolf
Added simple ice40 dff tests
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2015-04-16
Clifford Wolf
improved ice40 dff cell mapping
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2015-04-16
Clifford Wolf
Added "dff2dffe -direct-match"
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2015-04-14
Clifford Wolf
use "hierarchy -auto-top" in synth_ice40
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2015-04-14
Clifford Wolf
more cells in ice40 cell library
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2015-04-13
Clifford Wolf
Added "splice -wires"
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2015-04-13
Clifford Wolf
Added handling of bool-output cells to "wreduce"
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2015-04-09
Clifford Wolf
Improved xilinx "bram1" test
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2015-04-09
Clifford Wolf
Added memory_bram "make_outreg" feature
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2015-04-09
Clifford Wolf
Added back-end auto-detect for .edif and .json
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2015-04-09
Clifford Wolf
Minor fixes in handling of "init" attribute
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2015-04-09
Clifford Wolf
Xilinx DRAMS: RAM64X1D, RAM128X1D
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2015-04-09
Clifford Wolf
Fixed const2big performance bug
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2015-04-09
Clifford Wolf
techmap code cleanup
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2015-04-09
Clifford Wolf
Towards DRAM support in Xilinx flow
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2015-04-08
Clifford Wolf
Added support for "file names with blanks"
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2015-04-08
Clifford Wolf
Removed "techmap -share_map" (use "-map +/filename...
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2015-04-07
Clifford Wolf
Added %M and %C select operators
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2015-04-07
Clifford Wolf
Added "pmuxtree" command
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2015-04-07
Clifford Wolf
Added "chparam -list"
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2015-04-07
Clifford Wolf
Added decoder generation to "muxcover"
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2015-04-07
Clifford Wolf
Added hashlib support for std::tuple<>
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2015-04-07
Clifford Wolf
Added "muxcover" command
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2015-04-07
Clifford Wolf
Added pool<K>::pop()
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2015-04-07
Clifford Wolf
typo fix
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2015-04-07
Clifford Wolf
Added "chparam" command
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2015-04-06
Clifford Wolf
Added support for initialized xilinx brams
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2015-04-06
Clifford Wolf
Added support for initialized brams
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2015-04-06
Clifford Wolf
Added Xilinx test case for initialized brams
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2015-04-06
Clifford Wolf
Added Xilinx bram black-box modules
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2015-04-05
Clifford Wolf
Added "port_directions" to write_json output
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2015-04-05
Clifford Wolf
Avoid parameter values with size 0 ($mem cells)
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2015-04-05
Clifford Wolf
make all vector-size related integer params in $mem...
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2015-04-05
Clifford Wolf
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
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2015-04-04
Clifford Wolf
Added "dffinit", Support for initialized Xilinx DFF
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2015-04-04
Clifford Wolf
Added "init" attribute support to verilog backend
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2015-04-04
Clifford Wolf
appnote 012 fix
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2015-04-04
Clifford Wolf
Appnote 012
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2015-04-04
Clifford Wolf
Updated ABC to 51705b168d7a
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2015-04-04
Clifford Wolf
Merge pull request #55 from ahmedirfan1983/master
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2015-03-29
Clifford Wolf
documentation improvements
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2015-03-25
Clifford Wolf
Ignore celldefine directive in verilog front-end
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2015-03-25
Clifford Wolf
Fixes in cmos_cells.v
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