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Use reset signal from dramsync instead of sync
2020-07-02 Jean THOMASUse reset signal from dramsync instead of sync
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2020-07-02 Jean THOMASMake RefreshPostponer more similar to LiteDRAM's
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2020-07-02 Jean THOMASFix RefreshPostponer output stuck to 1
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2020-07-02 Jean THOMASFlatten specific parts of the designs
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2020-07-02 Jean THOMASAdd missing command issue strobe for ZQ calibration
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2020-07-02 Jean THOMASRemove PyYAML dependency
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2020-07-02 Jean THOMASFix register addresses, add missing command_issue strobe
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2020-07-02 Jean THOMASSet names to prevent CSR/DomainRenamer incompatibility
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2020-07-02 Jean THOMASAdd DDRDLLA patch
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2020-07-01 Jean THOMASFix merge
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2020-07-01 Jean THOMASRework indentation and add Wishbone tests
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2020-07-01 Jean THOMASAdd Wishbone interaction code
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2020-07-01 Jean THOMASAdd Wishbone interaction code
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2020-07-01 Jean THOMASFix Iverilog simulation
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2020-07-01 Jean THOMASGenerate ilang file
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2020-06-30 Jean THOMASBuild nMigen gateware in a specific folder
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2020-06-30 Jean THOMASRemove LED code in CRG
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2020-06-30 Jean THOMASRemove Minerva dependency
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2020-06-30 Jean THOMASApplying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
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2020-06-29 Jean THOMASDefine simulation time as a parameter
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2020-06-29 Jean THOMASDefine PLL's PHASELOADREG input
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2020-06-29 Jean THOMASUse -n option in vvp to enable CTRL+C
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2020-06-29 Jean THOMASFix PLL instanciation code for CRG simulation
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2020-06-29 Jean THOMASDump whole module
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2020-06-29 Jean THOMASFix DQSBUFM floating DYNDELAY
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2020-06-29 Jean THOMASSet DRAM's CK_N to low
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2020-06-29 Jean THOMASFix autopep8 madness
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2020-06-29 Jean THOMASUse BB instead of TRELLIS_IO
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2020-06-29 Jean THOMASFix CRG, revert to resetful sync domain
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2020-06-29 Jean THOMASSet UART RX to 1'b1
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2020-06-29 Jean THOMASAdd -Wall to simulations
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2020-06-26 Jean THOMASAdd testbench for SoC simulation
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2020-06-26 Jean THOMASUse FST instead of VCD
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2020-06-26 Jean THOMASExclude .fst files
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2020-06-26 Jean THOMASAdd DDRSoC simulation
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2020-06-26 Jean THOMASAdd gitignore for simulation folder
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2020-06-26 Jean THOMASFix PLL code
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2020-06-26 Jean THOMASAdd DRAM model
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2020-06-25 Jean THOMASFix typo
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2020-06-25 Jean THOMASAdd simulation code
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2020-06-25 Jean THOMASAdd README.md for gram tests
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2020-06-25 Jean THOMASAdd rddata_en, wrdata_mask tests
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2020-06-25 Jean THOMASAdd wrdata, wrdata_en tests to Phase Injector unit...
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2020-06-25 Jean THOMASFix R/W permissions to the bare minimum
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2020-06-25 Jean THOMASSet UART bridge SEL signals to 0xF
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2020-06-25 Jean THOMASAdd Wishbone read/write helpers
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2020-06-25 Jean THOMASUse constants for CSR addresses
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2020-06-25 Jean THOMASAdd bank address test
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2020-06-25 Jean THOMASFix DFII testing, test address set
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2020-06-24 Jean THOMASAdd buggy test for DFII
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2020-06-24 Jean THOMASFix CSR issue in PhaseInjector (r_data used for reading...
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2020-06-24 Jean THOMASFix CSR issue in DFII (r_data used for reading host...
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2020-06-24 Jean THOMASSimply arbiter when there is only 1 request to arbitrate
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2020-06-24 Jean THOMASEnsure we have at least one master
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2020-06-23 Jean THOMASOnly declare wants_zqcs signal if needed
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2020-06-23 Jean THOMASSimplify connections from refreshers to IOs (not FSM...
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2020-06-23 Jean THOMASRefactor test code
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2020-06-23 Jean THOMASFix DFII bitfield constants
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2020-06-23 Jean THOMASFix public libgram header
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2020-06-23 Jean THOMASCompile libgram as C99 code
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2020-06-23 Jean THOMASFix typo in GramWidth enum declaration
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2020-06-23 Jean THOMASFix ZQCSExecuter (set a signal to the proper size)...
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2020-06-23 Jean THOMASRefresher: fix a address size (fixes #14)
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2020-06-22 Jean THOMASRemove shadowing statement
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2020-06-22 Jean THOMASReplace bits_for with range
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2020-06-22 Jean THOMASRemove code for hybrid formal proof, unused
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2020-06-22 Jean THOMASRollback to the ECP5 P/N used in ECPIX-5
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2020-06-22 Jean THOMASFix pinout
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2020-06-22 Jean THOMASUse TRELLIS_IO instead of BB in ECP5 PHY
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2020-06-19 Jean THOMASUpdate memtest code in libgram
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2020-06-19 Jean THOMASRemove tests from gram.compat
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2020-06-19 Jean THOMASMove tests to a dedicated folder
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2020-06-18 Jean THOMASAdd unit tests for delayed_enter
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2020-06-18 Jean THOMASAdd test case for delayed_enter
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2020-06-18 Jean THOMASUse BB instance for bidirectionnal IOs
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2020-06-17 Jean THOMASRemove lambdasoc dependency from UARTBridge
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2020-06-17 Jean THOMASRollback PHY changes, use raw pins
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2020-06-16 Jean THOMASPartially fix the tristate IOs on DDR3 RAM
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2020-06-16 Jean THOMASFix oMigen cases and resource syntax
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2020-06-16 Jean THOMASFix old CSRStatus code
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2020-06-16 Jean THOMASFix variable read as an attribute
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2020-06-16 Jean THOMASUpdate switch to nMigen syntax
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2020-06-16 Jean THOMASFix CSR attribute error
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2020-06-16 Jean THOMASFix CSR attribute error
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2020-06-16 Jean THOMASFix pin count error (related to #9)
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2020-06-16 Jean THOMASFix pin count error (related to #9)
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2020-06-16 Jean THOMASExclude contrib/ and libgram/ from package installation
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2020-06-16 Jean THOMASPulse trigger signal rather than continuous trigger...
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2020-06-16 Jean THOMASAdd testing for Timeline elaboratable
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2020-06-16 Jean THOMASRemove VCD files
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2020-06-16 Jean THOMASRemove unused code
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2020-06-16 Jean THOMASReformulate GRAM_RW_FUNC section
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2020-06-16 Jean THOMASAdd example code for headless SoC
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2020-06-16 Jean THOMASAllow libgram to run outside a SoC
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2020-06-15 Jean THOMASFix autopep8 madness
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2020-06-15 Jean THOMASnMigen workaround: put default case at the end of the...
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2020-06-15 Jean THOMASInclude dash in compiler prefix variable
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2020-06-12 Jean THOMASFix clock signal for ECP5 PHY
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2020-06-12 Jean THOMASFix readout issue in Wishbone bridge (mentionned in #8)
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2020-06-12 Jean THOMASAdd while(1) loop to firmware
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