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Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes
2020-07-04
Eddie Hung
tests: update fsm.ys resource count
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2020-07-04
Eddie Hung
abc9: only techmap (* abc9_flop *) modules
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2020-07-04
Eddie Hung
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
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2020-07-04
Eddie Hung
abc9: techmap from user design to allow abc9_flop modules...
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2020-07-04
Eddie Hung
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
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2020-06-04
Eddie Hung
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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2020-06-04
Eddie Hung
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
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2020-06-03
Eddie Hung
tests: tidy up testcase
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2020-06-03
Eddie Hung
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
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2020-05-30
Eddie Hung
abc9_ops: fix comment
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2020-05-30
Eddie Hung
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast
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2020-05-30
Eddie Hung
abc9_ops: update messaging (credit to @Xiretza for...
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2020-05-30
Eddie Hung
abc9_ops: optimise to not derive unless attribute exists
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2020-05-30
Eddie Hung
abc9_ops: -reintegrate use SigMap to remove (* init...
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2020-05-25
Eddie Hung
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires...
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2020-05-25
Eddie Hung
xaiger: promote abc9_keep wires
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2020-05-25
Eddie Hung
tests: add ecp5 latch testcase with -abc9
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2020-05-25
Eddie Hung
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
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2020-05-25
Eddie Hung
blackbox: re-use existing Module::makeblackbox() method
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2020-05-25
Eddie Hung
tests: xilinx macc test to have initval, shorten BMC...
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2020-05-25
Eddie Hung
tests: fix some test warnings
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2020-05-25
Eddie Hung
xilinx: tidy up cells_sim.v a little
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2020-05-25
Eddie Hung
Merge pull request #2044 from YosysHQ/eddie/fix2037
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2020-05-25
Eddie Hung
tests: add test for abc9 -dff removing a redundant...
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2020-05-25
Eddie Hung
abc9_ops: -reintegrate to preserve flop names
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2020-05-25
Eddie Hung
tests: add testcase for abc9 -dff preserving flop names
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2020-05-25
Eddie Hung
aiger: cleanup
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2020-05-25
Eddie Hung
xaiger: cleanup
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2020-05-25
Eddie Hung
verilog: move attr from simple_behav_stmt to its children...
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2020-05-25
Eddie Hung
test: add attribute-before-stmt test from @nakengelhardt
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2020-05-25
Eddie Hung
verilog: do not warn for attributes on null statements
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2020-05-25
Eddie Hung
tests: add an generate-else test too
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2020-05-25
Eddie Hung
verilog: handle empty generate statement by removing...
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2020-05-25
Eddie Hung
verilog: fix #2037 by permitting (and freeing) attributes...
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2020-05-25
Eddie Hung
tests: add #2037 testcase
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2020-05-24
Eddie Hung
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
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2020-05-24
Eddie Hung
xaiger: add testcase
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2020-05-24
Eddie Hung
xaiger: do not derive cells
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2020-05-23
Eddie Hung
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
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2020-05-23
Eddie Hung
ecp5: cleanup unused +/ecp5/abc9_model.v
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2020-05-22
Eddie Hung
abc9_ops: update comment
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2020-05-21
Eddie Hung
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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2020-05-21
Eddie Hung
Update frontends/verilog/verilog_parser.y
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2020-05-18
Eddie Hung
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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2020-05-15
Eddie Hung
verific: rewrite initial assume/asserts prior to elaboration
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2020-05-14
Eddie Hung
abc9: use (* abc9_keep *) instead of (* abc9_scc *...
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2020-05-14
Eddie Hung
verilog: attributes before task enable (but 13 s/r...
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2020-05-14
Eddie Hung
tests: attributes before task enable
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2020-05-14
Eddie Hung
Merge pull request #2055 from YosysHQ/eddie/logger_multiple
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2020-05-14
Eddie Hung
techmap: sort celltypeMap as it determines techmap...
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2020-05-14
Eddie Hung
techmap: prefix special wires with backslash for use...
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2020-05-14
Eddie Hung
opt_expr: Sx to Sz; spotted by @Xiretza
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2020-05-14
Eddie Hung
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758
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2020-05-14
Eddie Hung
logger: clean up doc
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2020-05-14
Eddie Hung
abc9_ops: -prep_hier to create unmap module that removes...
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2020-05-14
Eddie Hung
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean...
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2020-05-14
Eddie Hung
Fix broken test when ignoring abc9_flop with init ...
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2020-05-14
Eddie Hung
abc9_ops/xaiger: further reducing Module::derive()...
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2020-05-14
Eddie Hung
Cleanup; reduce Module::derive() calls
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2020-05-14
Eddie Hung
ecp5: latches_map.v if *not* -asyncprld
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2020-05-14
Eddie Hung
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un...
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2020-05-14
Eddie Hung
ecp5: fix rebase mistake
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2020-05-14
Eddie Hung
abc9: update to =_$abc9_flops pattern which includes...
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2020-05-14
Eddie Hung
abc9_ops: update docs
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2020-05-14
Eddie Hung
xilinx: gate specify/attributes from iverilog
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2020-05-14
Eddie Hung
abc9: only do +/abc9_map if `DFF
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2020-05-14
Eddie Hung
abc9: rework submod -- since it won't move (* keep...
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2020-05-14
Eddie Hung
ecp5: TRELLIS_FF bypass path only in async mode
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2020-05-14
Eddie Hung
timinginfo: ignore $specify2 cells if EN is false
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2020-05-14
Eddie Hung
xilinx/ice40/ecp5: zinit requires selected wires, so...
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2020-05-14
Eddie Hung
abc9_ops: move assert
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2020-05-14
Eddie Hung
abc9: put 'aigmap' back
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2020-05-14
Eddie Hung
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able...
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2020-05-14
Eddie Hung
abc9_ops: fix bypass boxes using (* abc9_bypass *)
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2020-05-14
Eddie Hung
abc9_ops: tidy up, suppress error if no boxes/holes
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2020-05-14
Eddie Hung
abc9_ops: -prep_delays to not insert delay box if input...
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2020-05-14
Eddie Hung
abc9_ops: cleanup; -prep_dff -> -prep_dff_submod
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2020-05-14
Eddie Hung
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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2020-05-14
Eddie Hung
abc9_ops: -reintegrate to handle $_FF_; cleanup
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2020-05-14
Eddie Hung
xaiger: no longer use nonstandard even/odd to designate...
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2020-05-14
Eddie Hung
aiger: -xaiger to return $_FF_ flops
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2020-05-14
Eddie Hung
abc9: not enough to techmap_fail on (* init=1 *), hide...
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2020-05-14
Eddie Hung
abc9: test to use box file instead of auto
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2020-05-14
Eddie Hung
abc9: restore selected_modules()
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2020-05-14
Eddie Hung
synth_*: no need to explicitly read +/abc9_model.v
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2020-05-14
Eddie Hung
Revert "Merge pull request #1917 from YosysHQ/eddie...
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2020-05-14
Eddie Hung
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
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2020-05-14
Eddie Hung
kernel: TimingInfo to clamp -ve setup/edge-sensitive...
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2020-05-14
Eddie Hung
abc9_ops: -prep_dff_map to error if async flop found
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2020-05-14
Eddie Hung
Uncomment negative setup times; clamp to zero for connectivity
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2020-05-14
Eddie Hung
abc9: remove redundant wbflip
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2020-05-14
Eddie Hung
xaiger: always sort input/output bits by port id
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2020-05-14
Eddie Hung
abc9: generate $abc9_holes design instead of <name...
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2020-05-14
Eddie Hung
abc9_ops: more robust
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2020-05-14
Eddie Hung
abc9: suppress warnings when no compatible + used flop...
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2020-05-14
Eddie Hung
xilinx: update abc9_dff tests
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2020-05-14
Eddie Hung
xilinx: remove no-longer-relevant test
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2020-05-14
Eddie Hung
aiger/xaiger: use odd for negedge clk, even for posedge
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2020-05-14
Eddie Hung
abc9: cleanup
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2020-05-14
Eddie Hung
Revert "ecp5: replace ecp5_ffinit with techmap rules...
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