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Fix wrong T1 signal
2020-07-27 Jean THOMASFix wrong T1 signal
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2020-07-27 Jean THOMASAdd comment
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2020-07-27 Jean THOMASAdd sublime-project file
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2020-07-27 Jean THOMASAdd Precharge-For-Refresh state
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2020-07-27 Jean THOMASRemove reference to UART
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2020-07-27 Jean THOMASWire directly to the Wishbone bus, making simulations...
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2020-07-24 Jean THOMASUse Yices from Fedora repository
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2020-07-24 Jean THOMASRemove unnecessary modules in gram tests
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2020-07-24 Jean THOMASAdd test for tFAWController
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2020-07-24 Jean THOMASAdd memtest score
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2020-07-24 Jean THOMASFix tXXDController (was overflowing)
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2020-07-24 Jean THOMASUse Z3 from Fedora repos for faster CI
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2020-07-24 Jean THOMASExpose gram_reset_burstdet and gram_read_burstdet APIs
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2020-07-24 Jean THOMASFix code styling
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2020-07-24 Jean THOMASRemoving superfluous variables in multiplexer
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2020-07-24 Jean THOMASRemove commented test
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2020-07-24 Jean THOMASFix code styling
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2020-07-24 Jean THOMASFix AntiStarvation
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2020-07-24 Jean THOMASUse the correct value for test depth
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2020-07-23 Jean THOMASParametric test size, add delay option between write...
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2020-07-23 Jean THOMASRevert to timings from LiteDRAM
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2020-07-23 Jean THOMASFix code styling
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2020-07-23 Jean THOMASUse clk pin definition from upstream nmigen-boards
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2020-07-23 Jean THOMASUpdate nMigen version requirement
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2020-07-23 Jean THOMASFix burstdet CSR code
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2020-07-23 Jean THOMASFix platform code for simulation
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2020-07-22 Jean THOMASRemove DQSPattern import
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2020-07-22 Jean THOMASAdd notes regarding CI usage
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2020-07-22 Jean THOMASHandle rdly customization
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2020-07-22 Jean THOMASRemove unnecessary signal reset
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2020-07-22 Jean THOMASRework burstdet CSR code
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2020-07-22 Jean THOMASFix granularity and sel in UARTBridge
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2020-07-22 Jean THOMASFix ECPIX585Platform to work with the latest commits...
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2020-07-21 Jean THOMASRework CSR interface for PHY
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2020-07-21 Jean THOMASUse 0x00BA0BAB instead of 0x12345678 for better readability
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2020-07-21 Jean THOMASRemove commented DDR3 resource definition
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2020-07-21 Jean THOMASFix write timings
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2020-07-21 Jean THOMASReplace Switch with If statement, indentation fixup
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2020-07-20 Jean THOMASRemove DQSPattern
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2020-07-20 Jean THOMASApply changes from LiteDRAM#fa7d91a
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2020-07-20 Jean THOMASFix code styling
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2020-07-20 Jean THOMASAdding test for tXXDController
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2020-07-20 Jean THOMASAdd simple test for DQSPattern
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2020-07-20 Jean THOMASDisable SSH access for successful builds
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2020-07-20 Jean THOMASSimplify parameters code for DQSPattern
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2020-07-20 Jean THOMASRemove unused code (PHYPadsCombiner/PHYPadsReducer)
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2020-07-20 Jean THOMASFix code styling
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2020-07-20 Jean THOMASSet SEL when reading
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2020-07-20 Jean THOMASRemove useless signal
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2020-07-20 Jean THOMASUse PinsN when possible (fixes #27)
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2020-07-20 Jean THOMASSimplify PHY read code
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2020-07-17 Jean THOMASUse XDR for RAS#, CAS#, WE#, CLK_EN and ODT
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2020-07-17 Jean THOMASCode cleaning in ECP5 PHY
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2020-07-17 Jean THOMASUse XDR for ba pins
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2020-07-17 Jean THOMASUse XDR for address pins
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2020-07-17 Jean THOMASFix when there are multiple clocks
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2020-07-17 Jean THOMASUse nMigen's XDR for DDR clk
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2020-07-17 Jean THOMASRemove unused signal
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2020-07-17 Jean THOMASFix code styling
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2020-07-17 Jean THOMASRemove adaptation code
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2020-07-17 Jean THOMASRemove get_port() function
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2020-07-17 Jean THOMASAdd test for _AntiStarvation timer duration
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2020-07-17 Jean THOMASFix code styling
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2020-07-17 Jean THOMASUse the right domain
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2020-07-17 Jean THOMASFix PHY issues
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2020-07-17 Jean THOMASReduce delay between wishbone_write
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2020-07-17 Jean THOMASFactor MRx setting code
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2020-07-17 Jean THOMASLog DRAM commands
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2020-07-17 Jean THOMASPut proc_rmdead after proc_mux
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2020-07-17 Jean THOMASName each BankMachine instance to improve VCD output
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2020-07-17 Jean THOMASFix CRG parameters
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2020-07-17 Jean THOMASFix DQS_N errors
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2020-07-17 Jean THOMASAdd more read transactions, add checks, ASAP
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2020-07-17 Jean THOMASRemove event in ECP5DDRPHY
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2020-07-17 Jean THOMASRemove comment
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2020-07-16 Jean THOMASUse assertions in simsoc testbench
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2020-07-16 Jean THOMASAdd logging and delays to the simulation to make it...
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2020-07-16 Jean THOMASTweak yosys script
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2020-07-16 Jean THOMASBackport modifications from example's CRG
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2020-07-15 Jean THOMASWrite logic equivalences in a clearer way
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2020-07-15 Jean THOMASMake Micron model read the mem_init.txt file
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2020-07-15 Jean THOMASMake gram simulations faster
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2020-07-15 Jean THOMASAdd initial memory content
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2020-07-15 Jean THOMASAdd early code for RAM calibration
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2020-07-15 Jean THOMASExpose DFII functions to other objects
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2020-07-15 Jean THOMASIncrease UART bridge speed in simulation, decrease...
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2020-07-15 Jean THOMASLog RAM signals
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2020-07-15 Jean THOMASFix code styling
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2020-07-15 Jean THOMASRemove arbiter from headless-ecpix5 example
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2020-07-15 Jean THOMASUse random values for memtest
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2020-07-13 Jean THOMASPer bytes error highlighting
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2020-07-13 Jean THOMASMake _AddressSlicer an elaboratable
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2020-07-13 Jean THOMASUpdate amount of tests
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2020-07-13 Jean THOMASRemove unnecessary arbiter
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2020-07-13 Jean THOMASFix timings in libgram
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2020-07-13 Jean THOMASReduce POR duration
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2020-07-13 Jean THOMASFix gearing and UART speed
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2020-07-13 Jean THOMASAdd additional opt+clean and print stats
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2020-07-13 Jean THOMASMake full use of the native port
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2020-07-13 Jean THOMASFix gearing
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