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CPU/Cache: Fix some errors exposed by valgrind
2010-08-26
Gene WU
ARM: Seperate the queues of L1 and L2 walker states.
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2010-08-26
Gene WU
ARM: Use fewer micro-ops for register update loads...
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2010-08-23
Gene Wu
ARM: Implement DBG instruction that doesn't do much...
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2010-08-23
Gene Wu
MEM: Make CLREX a first class request operation and...
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2010-08-23
Gene Wu
ARM: Make sure that software prefetch instructions...
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2010-08-23
Gene Wu
ARM: Don't write tracedata on writes, it might have...
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2010-08-23
Gene Wu
ARM: Implement CLREX init/complete acc methods
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2010-08-23
Gene Wu
ARM: Fix Uncachable TLB requests and decoding of xn bit
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2010-08-23
Gene Wu
Devices: Allow a device to specify that a request is...
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2010-08-23
Gene Wu
ARM: For non-cachable accesses set the UNCACHABLE flag
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2010-08-23
Gene Wu
ARM: Implement DSB, DMB, ISB
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2010-08-23
Gene Wu
ARM: Get SCTLR TE bit from reset SCTLR
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2010-08-23
Gene Wu
ARM: Implement CLREX
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2010-08-23
Gene Wu
ARM: BX instruction can be contitional if last instruction...
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2010-08-23
Gene Wu
ARM: DFSR status value for sync external data abort...
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2010-08-23
Gene Wu
ARM: Temporary local variables can't conflict with...
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