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tests: mmu: Add tests for instruction translation
2020-05-08 Paul Mackerrastests: mmu: Add tests for instruction translation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Do radix page table walks on iTLB misses
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd TLB to icache
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrastests: Add a test for the MMU radix page table walks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Remove software-loaded dTLB mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Refetch PTE on access fault
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement data segment interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasMMU: Implement radix page table machinery
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasAdd framework for implementing an MMU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement access permission checks
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement data storage interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdcache: Implement data TLB
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasPass mtspr/mfspr to MMU-related SPRs down to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasmw_debug: Add support for reading GSPRs and writing...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdebug: Provide a way to examine GPRs, fast SPRs and MSR
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImprove architectural compliance of mfspr and mtspr
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul Mackerrasdecode1: Implement eieio as a nop
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-08 Paul MackerrasImplement the extswsli instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerrasexecute1: Fix interrupt delivery during slow instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul Mackerraswishbone_debug_master: Fix address auto-increment for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-05-06 Paul MackerrasMerge remote-tracking branch 'remotes/origin/master'
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2020-05-06 Paul Mackerrasdcache: Don't assert on dcbz cache hit
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasChange the default cross compiler prefix to powerpc64le...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul MackerrasMakefile: fix typo
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-29 Paul Mackerrastests: Add a test for privileged instruction interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasdcache: Implement the dcbz instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul MackerrasPlumb insn_type through to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Generate privileged instruction interrupts...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-28 Paul Mackerrasexecute1: Improve architecture compliance of MSR and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-22 Paul Mackerrasexecute1: Don't execute ld/st instruction when taking...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasDecode attn in the major opcode decode table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasDecode sc in the major opcode decode table
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasRemove sim_config instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrasexecute1: Implement trap instructions properly
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasConsolidate trap variants under a single OP_TRAP
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrasexecute1: Simplify the interrupt logic a little
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul MackerrasRename OP_MCRF to OP_CROP and trim insn_type_t
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-07 Paul Mackerrastests: Put an attn instruction at 0x700
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul MackerrasGive exceptions a separate path to writeback
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrastests: Update executables
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrastests: Adjust header inclusions and Makefile.test
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrashello_world: Use ldcix/stdcix to access UART
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-04-03 Paul Mackerrashello_world: Adjust header inclusions and Makefile
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-30 Paul Mackerrasloadstore1: Add support for cache-inhibited load and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-29 Paul Mackerrasloadstore1: Move load data formatting from writeback...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-28 Paul Mackerrasloadstore1: Move logic from dcache to loadstore1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-05 Paul Mackerrasdcache: Remove LOAD_UPDATE2 state
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-03-04 Paul Mackerrasdcache: Trim one cycle from the load hit path
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-27 Paul Mackerrasdcache: Implement load-reserve and store-conditional...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-26 Paul Mackerrasdcache: Add support for unaligned loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-21 Paul Mackerrasdcache: Fix obscure bug and minor cleanups
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-19 Paul MackerrasRemove single-issue constraint for most loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-02-05 Paul Mackerrasexecute1: Use truth table embedded in instruction for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasdecode1: Mark subfic as pipelined
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrascountzero: Add a register to help make timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul MackerrasPlumb loadstore1 input from execute1 not decode2
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasexecute: Implement bypass from output of execute1 to...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasexecute: Move popcnt and prty instructions into the...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasexecute: Do comparisons using the main adder
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasexecute1: Move EXTS* instruction back into execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul Mackerrasexecute1: Remember dest GPR, RC, OE, XER for slow operations
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul MackerrasMake divider hang off the side of execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-01-14 Paul MackerrasMake multiplier hang off the side of execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Paul Mackerrasdecode2: Minor cleanup
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Benjamin Herrenschmidtsprs: Store common SPRs in register file
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Benjamin Herrenschmidtspr: Add translation from SPR to special GPR number
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Paul Mackerrasdivider: Fix overflow calculation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Paul Mackerrasdecode1: Add OE=1 forms of add/sub, mul and div instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Paul Mackerrasexecute: Copy XER[SO] to CR for cmp[i] and cmpl[i]...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-07 Benjamin HerrenschmidtAdd basic XER support
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-05 Benjamin Herrenschmidtdecode1: Mark ALU ops using carry as pipelined
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-12-05 Benjamin Herrenschmidtcr_file: Check write_cr_enable
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul Mackerraswriteback: Eliminate inferred latch
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul Mackerraswishbone_debug_master: Improve timing
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul MackerrasRemove execute2 stage
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul MackerrasDo sign-extension instructions in writeback instead...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul Mackerraswriteback: Do data formatting and condition recording...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul MackerrasImplement neg using OP_ADD
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-15 Paul Mackerrasdivider: Reduce delay in detecting 32-bit overflow
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-14 Paul Mackerrasdivider: Add an output register
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-13 Paul Mackerrascountzero: Add a testbench
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-13 Paul Mackerrascountzero: Reorganize to have fewer levels of logic...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-12 Paul Mackerrasdivider: Return 0 for invalid and overflow cases, like...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-12 Paul Mackerrasdecode2: Fix 32-bit flag passed to divider
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-08 Paul Mackerrasexecute: Consolidate count-leading/trailing-zeroes...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-07 Paul MackerrasAdd a rotate/mask/shift unit and use it in execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-07 Paul MackerrasGeneralize the mul_32bit and mul_signed fields of decode_rom_t
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-04 Paul Mackerrasdecode: Avoid multiplexing from instruction reg fields...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-04 Paul MackerrasConsolidate add/subtract instructions into a single op
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-03 Paul Mackerrasdecode: Make all update-form indexed loads and stores...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-02 Paul Mackerrasdecode: Remove const fields from decode_rom_t
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Fix larx/stcx instructions to use RA_OR_ZERO...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Index minor op table with insn bits for opcode 31
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Index minor op table with insn bits for opcode 30
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Index minor op table with insn bits for opcode 19
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Start moving towards decoding by major opcode...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Paul Mackerrasdecode: Push mtspr/mfspr register decoding down into...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2019-10-01 Benjamin HerrenschmidtAdd MCRF instruction
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2019-10-01 Benjamin HerrenschmidtImplement absolute branches
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2019-09-27 Paul Mackerrasfpga: Add definitions for Arty A7-100 board
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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