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Fix attributes on $__ABC9_ASYNC[01] whitebox
2019-12-28
Miodrag Milanovic
Fix new tests
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2019-12-28
Miodrag Milanovic
Merge remote-tracking branch 'origin/master' into iopad_default
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2019-12-28
Miodrag Milanovic
Make test without iopads
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2019-12-28
Miodrag Milanovic
Revert "Fix xilinx tests, when iopads are default"
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2019-12-25
Miodrag Milanovic
fixed invalid char
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2019-12-21
Miodrag Milanovic
Addressed review comments
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2019-12-21
Miodrag Milanovic
iopad no op for compatibility with old scripts
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2019-12-21
Miodrag Milanovic
Fix xilinx tests, when iopads are default
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2019-12-21
Miodrag Milanovic
Make iopad option default for all xilinx flows
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2019-11-11
Miodrag Milanovic
Fixed tests
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2019-10-18
Miodrag Milanovic
fixed error
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2019-10-18
Miodrag Milanovic
Unify verilog style
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2019-10-18
Miodrag Milanovic
Common memory test now shared
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2019-10-18
Miodrag Milanovic
Remove not needed tests
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2019-10-18
Miodrag Milanovic
Share common tests
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2019-10-18
Miodrag Milanovic
fix yosys path
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2019-10-18
Miodrag Milanovic
Fix path to yosys
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2019-10-18
Miodrag Milanovic
Moved all tests in arch sub directory
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2019-10-18
Miodrag Milanovic
Add async2sync
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-18
Miodrag Milanovic
hierarchy - proc reorder
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2019-10-17
Miodrag Milanovic
Make equivalence work with latest master
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2019-10-17
Miodrag Milanovic
remove not needed top module
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2019-10-17
Miodrag Milanovic
remove not needed top module
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2019-10-17
Miodrag Milanovic
split muxes synth per type
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2019-10-17
Miodrag Milanovic
Test dffs separetely
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2019-10-17
Miodrag Milanovic
Split latches into separete tests
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2019-10-17
Miodrag Milanovic
Fix formatting
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2019-10-17
Miodrag Milanovic
Clean verilog code from not used define block
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2019-10-17
Miodrag Milanovic
Removed alu and div_mod test as agreed, ignore generated...
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2019-10-17
Miodrag Milanovic
Test per flip-flop type
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2019-10-04
Miodrag Milanovic
Fixes for MSVC build
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2019-10-04
Miodrag Milanovic
FF should be initialized to 0
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2019-10-04
Miodrag Milanovic
Split mux tests per type
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2019-10-04
Miodrag Milanovic
Split latch check
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2019-10-04
Miodrag Milanovic
Add missing latch mapping
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2019-10-04
Miodrag Milanovic
split rest od ff's
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2019-10-04
Miodrag Milanovic
Separate check for ff's types
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2019-10-04
Miodrag Milanovic
Cleaned tests
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2019-10-04
Miodrag Milanovic
Remove not needed tests
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2019-10-04
Miodrag Milanovic
Merge branch 'SergeyDegtyar/efinix' of https://github...
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2019-10-04
Miodrag Milanovic
Cleanup and formating
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2019-10-04
Miodrag Milanovic
split latches into separate checks
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2019-10-04
Miodrag Milanovic
check muxes per type
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2019-10-04
Miodrag Milanovic
check ff's separately
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2019-10-04
Miodrag Milanovic
Cleanup top modules and not used defines
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2019-10-04
Miodrag Milanovic
remove alu test
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2019-10-04
Miodrag Milanovic
Merge branch 'SergeyDegtyar/anlogic' of https://github...
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2019-10-04
Miodrag Milanovic
Check latches type one by one
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2019-10-04
Miodrag Milanovic
Removed top module where not needed
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2019-10-04
Miodrag Milanovic
Test muxes synth one by one
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2019-10-04
Miodrag Milanovic
Cleaned verilog code from not used defines
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2019-10-04
Miodrag Milanovic
Check for MULT18X18D, since that is working now
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2019-10-04
Miodrag Milanovic
Check flops one by one
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2019-10-04
Miodrag Milanovic
Removed alu and div_mod tests as agreed
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2019-10-01
Miodrag Milanovic
Define environ, fixes #1424
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2019-09-29
Miodrag Milanovic
Fix reading aig files on windows
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2019-09-29
Miodrag Milanovic
Open aig frontend as binary file
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2019-09-28
Miodrag Milanovic
Add aiger and protobuf backends binary support
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2019-09-28
Miodrag Milanovic
Support binary files for backends, fixes #1407
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2019-09-27
Miodrag Milanovic
Change order of parameters, to work on other os
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2019-09-26
Miodrag Milanovic
Make read/write gzip files on macos works, fixes #1357
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2019-09-18
Miodrag Milanovic
make note that it is for latch mode
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2019-09-18
Miodrag Milanovic
better lut handling
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2019-09-18
Miodrag Milanovic
better handling of lut and begin/end add
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2019-09-15
Miodrag Milanovic
Added simulation models for Efinix and Anlogic
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2019-09-01
Miodrag Milanovic
Fix select command error msg, fixes issue #1081
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2019-08-31
Miodrag Milanovic
Fix TRELLIS_FF simulation model
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-23
Miodrag Milanovic
Make macOS depenency clear
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-22
Miodrag Milanovic
do not require boost if pyosys is not used
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2019-08-21
Miodrag Milanovic
Fix test_pmgen deps
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2019-08-18
Miodrag Milanovic
Merge remote-tracking branch 'upstream/master' into...
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2019-08-18
Miodrag Milanovic
Ignore all generated headers for pmgen pass
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2019-08-16
Miodrag Milanovic
Regression in abc9
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2019-08-16
Miodrag Milanovic
Just needed IDs to be IdString
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2019-08-12
Miodrag Milanovic
Proper arith for Anlogic and use standard pass
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2019-08-11
Miodrag Milanovic
Fix formating
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2019-08-11
Miodrag Milanovic
one bit enable signal
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2019-08-11
Miodrag Milanovic
fix mixing signals on FF mapping
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2019-08-11
Miodrag Milanovic
Replaced custom step with setundef
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2019-08-11
Miodrag Milanovic
Fixed data width
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2019-08-11
Miodrag Milanovic
Adding new pass to fix carry chain
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2019-08-11
Miodrag Milanovic
cleanup
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2019-08-09
Miodrag Milanovic
Fix CO
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2019-08-09
Miodrag Milanovic
Merge remote-tracking branch 'upstream/master' into...
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2019-08-09
Miodrag Milanovic
ABC requires it like this
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2019-08-09
Miodrag Milanovic
Propagate parameters for Travis build
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2019-08-04
Miodrag Milanovic
clock for ram trough gbuf
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2019-08-04
Miodrag Milanovic
Added bram support
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2019-08-03
Miodrag Milanovic
anlogic : Fix alu mapping
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2019-08-03
Miodrag Milanovic
Custom step to add global clock buffers
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2019-08-03
Miodrag Milanovic
Initial EFINIX support
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2019-08-02
Miodrag Milanovic
Visual Studio build fix
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2019-08-02
Miodrag Milanovic
Fix linking issue for new mxe and pthread
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2019-08-02
Miodrag Milanovic
Fix yosys linking for mxe
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2019-08-02
Miodrag Milanovic
New mxe hacks needed to support 2ca237e
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