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Add Tercel support to Arty
2021-01-19 Paul Mackerrascore: Allow multiple loadstore instructions to be in...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-19 Paul Mackerrasloadstore: Convert to 3-stage pipeline
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-19 Paul Mackerrasdcache: Fix bugs in pipelined operation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-19 Paul Mackerrascore: Send FPU interrupts to writeback rather than...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Send loadstore1 interrupts to writeback rather...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Move redirect and interrupt delivery logic to...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrasexecute1: Move CR result to data path process
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrasexecute1: Move data-path logic out to a separate process
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Track CR hazards and bypasses using tags
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Restore bypass path from execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Track GPR hazards using tags that propagate through...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Crack branches that update both CTR and LR
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrascore: Crack update-form loads into two internal ops
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-18 Paul Mackerrasfetch1: Implement a simple branch target cache
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasexecute1: Improve timing on comparisons
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrascore: Reorganize execute1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdecode1: Implement tlbsync as a no-op
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrascore: Make result multiplexing explicit
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdecode1: Implement obsolete dst, dstst, dss instructions...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasexecute1: Move branch adder after register
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdecode: Add a facility field to the instruction decode...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdecode1: Take an extra cycle for predicted branch redirects
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrastests: Add tests for lq/stq and lqarx/stqcx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasloadstore1/dcache: Send store data one cycle later
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrascore: Implement quadword loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasloadstore1: Improve timing of data path from cache...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdcache: Add more commentary, no code change
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasloadstore1: Decide on load formatting controls a cycle...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasdecode1: Fix decoding of recommended NOP instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrascore_debug: Stop logging 256 cycles after trigger
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrascore_debug: Add an address trigger to stop logging...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul MackerrasFPU: Don't use mask generator for rounding
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul MackerrasFPU: Relax timing around multiplier output
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasmw_debug: Display terminated status when stopping
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasmw_debug: Extend to handle FPRs
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul MackerrasArty A7: Document pin connections for on-board headers
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-15 Paul Mackerrasexecute1: Update comments about XER forwarding
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2021-01-07 Paul MackerrasMerge pull request #263 from antonblanchard/reset-pid
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2021-01-07 Paul MackerrasMerge pull request #262 from antonblanchard/reset-tb...
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2021-01-07 Paul MackerrasMerge pull request #259 from antonblanchard/dmi-reset
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2020-12-19 Paul Mackerrasfetch1: Fix debug stop
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-12-17 Paul Mackerrassoc: Drive uart1_irq to 0 when we don't have UART1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-12-14 Paul MackerrasMerge pull request #257 from antonblanchard/nofpu-fix
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2020-11-24 Paul Mackerrastests/misc: Add a test for correct CTR and LR updating...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-24 Paul Mackerrasexecute1: Fix forwarding of result when doing delayed...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-21 Paul Mackerrasexecute1: Fix writing LR for bdnzl/bdzl instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-11-21 Paul Mackerrascore: Implement mtmsr instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-10-05 Paul Mackerrastests/trace: Test trace interrupt vs. FP unavailable...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-10-03 Paul Mackerrasexecute1: Fix bug in trace interrupt vs. ITLB miss
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-12 Paul MackerrasFPU: Do masking after adder rather than on A input
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Decide on mask length a cycle earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Decide on A input selection a cycle earlier
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Add comments specifying the expectation of r.shift...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating multiply-add instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement ftdiv and ftsqrt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fsqrt[s] and add a test for fsqrt
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement frsqrte[s] and a test for frsqrte
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for fsel and fcmpu
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fcmpu and fcmpo
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fsel
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fre[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fdiv[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmul[s]
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fadd[s] and fsub[s] and add tests for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmrgew and fmrgow and add tests for...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating round-to-integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating convert to integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for frsp
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement the frsp instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement floating convert from integer instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement fmr and related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Test remaining FPSCR-related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul MackerrasFPU: Implement remaining FPSCR-related instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for basic FPSCR function and interrupt...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add framework for an FPU
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests/fpu: Add tests for lfs and stfs instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add support for single-precision FP loads and...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrastests: Add a test for FP loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-09-03 Paul Mackerrascore: Add support for floating-point loads and stores
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrastests: Add a test for trace interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrasexecute1: Implement trace interrupts
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-29 Paul Mackerrasdecode1: Avoid overriding fields of v.decode in decode1
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrastests: Add a test for the load-reserve and store-conditional...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrasloadstore1: Generate alignment interrupts for unaligned...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-22 Paul Mackerrastests: Add tests for 32-bit and big-endian modes
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrascore: Implement 32-bit mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrascore: Implement big-endian mode
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-20 Paul Mackerrastests/mmu: Update to use correct MSR values
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-07 Paul Mackerrascore: Implement BCD Assist instructions addg6s, cdtbcd...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the wait instruction as a no-op
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the reserved no-op instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the addex instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the maddhd, maddhdu and maddld instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the cmpeqb and cmprb instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the bpermd instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the setb instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-06 Paul Mackerrascore: Implement the mcrxrx instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrascore: Implement the TAR register and the bctar instruction
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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2020-08-05 Paul Mackerrasexecute1: Use r.<field> not v.<field> in countzero...
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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