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| 2021-01-20 | Claire Xen | Merge pull request #2552 from YosysHQ/claire/yosyshq |
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| 2021-01-20 | Claire Xenia Wolf | Switch verific bindings from Symbiotic EDA flavored... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> |
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| 2021-01-13 | Claire Xen | Merge pull request #2537 from pepijndevos/spice |
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| 2020-12-27 | Claire Xen | Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS... |
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| 2020-12-01 | Claire Xen | Merge pull request #2463 from georgerennie/fix_verilog_front... |
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| 2020-11-25 | Claire Xen | Merge pull request #2133 from dh73/nodev_head |
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| 2020-10-19 | Claire Xenia Wolf | Fix argument handling in connect_rpc Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com> |
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| 2020-10-01 | Claire Xenia Wolf | Ignore empty parameters in Verilog module instantiations Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com> |
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