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i965/vec4: fix store output for 64-bit types
2017-01-03 Iago Toral Quirogai965/vec4: fix store output for 64-bit types
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2017-01-03 Iago Toral Quirogai965/vec4: fix attribute setup for doubles
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2017-01-03 Iago Toral Quirogai965/vec4: fix indentation in lower_attributes_to_hw_regs()
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2017-01-03 Iago Toral Quirogai965/vec4: make emit_pull_constant_load support 64...
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2017-01-03 Iago Toral Quirogai965/vec4: fix move_push_constants_to_pull_constants...
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2017-01-03 Iago Toral Quirogai965/vec4: fix indentation in move_push_constants_to_pull_co...
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2017-01-03 Iago Toral Quirogai965/vec4: fix move_uniform_array_access_to_pull_constant...
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2017-01-03 Iago Toral Quirogai965/vec4: fix scratch writes for 64bit data
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2017-01-03 Iago Toral Quirogai965/vec4: fix scratch reads for 64bit data
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2017-01-03 Iago Toral Quirogai965/vec4: fix scratch offset for 64bit data
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2017-01-03 Iago Toral Quirogai965/vec4: do not split scratch read/write opcodes
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2017-01-03 Iago Toral Quirogai965/vec4: Do not use DepCtrl with 64-bit instructions
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2017-01-03 Iago Toral Quirogai965/vec4: extend the DWORD multiply DepCtrl restriction...
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2017-01-03 Samuel Iglesias... i965/vec4: don't copy propagate misaligned registers
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: don't propagate single-precision uniforms...
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2017-01-03 Iago Toral Quirogai965/vec4: Prevent copy propagation from violating...
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2017-01-03 Iago Toral Quirogai965/vec4: prevent copy-propagation from values with...
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2017-01-03 Connor Abbotti965/vec4: don't constant propagate 64-bit immediates
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: Fix SSBO stores for 64-bit data
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2017-01-03 Iago Toral Quirogai965/vec4: Fix SSBO loads for 64-bit data
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2017-01-03 Iago Toral Quirogai965/vec4: Fix UBO loads for 64-bit data
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2017-01-03 Iago Toral Quirogai965/vec4: Add a shuffle_64bit_data helper
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2017-01-03 Iago Toral Quirogai965/vec4: support multiple dispatch widths and groups...
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2017-01-03 Iago Toral Quirogai965/vec4: Lower 64-bit MAD
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4/nir: do not emit 64-bit MAD
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2017-01-03 Iago Toral Quirogai965/vec4: Skip swizzle to subnr in 3src instructions...
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2017-01-03 Iago Toral Quirogai965/vec4: fix indentation in pack_uniform_registers
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2017-01-03 Iago Toral Quirogai965/vec4: fix pack_uniform_registers for doubles
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2017-01-03 Iago Toral Quirogai965/vec4: teach register coalescing about 64-bit
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2017-01-03 Iago Toral Quirogai965/disasm: fix subreg for dst in Align16 mode
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2017-01-03 Iago Toral Quirogai965/vec4: implement access to DF source components Z/W
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2017-01-03 Iago Toral Quirogai965/vec4: translate 64-bit swizzles to 32-bit
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: add a scalarization pass for double-precision...
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2017-01-03 Iago Toral Quirogai965/vec4: split double-precision SEL
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2017-01-03 Iago Toral Quirogai965/vec4: teach cmod propagation about different execution...
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2017-01-03 Iago Toral Quirogai965/vec4: teach CSE about exec_size, group and doubles
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2017-01-03 Iago Toral Quirogai965/disasm: print NibCtrl for instructions with execsize < 8
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2017-01-03 Iago Toral Quirogai965/vec4: dump NibCtrl for instructions with execsize...
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2017-01-03 Iago Toral Quirogai965/vec4: make the generator set correct NibCtrl for...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: add a SIMD lowering pass
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2017-01-03 Iago Toral Quirogai965: move the group field from fs_inst to backend_instruction.
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2017-01-03 Iago Toral Quirogai965/vec4: add a horiz_offset() helper
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2017-01-03 Juan A. Suarez Romeroi965/vec4: handle 32 and 64 bit channels in liveness...
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2017-01-03 Iago Toral Quirogai965/vec4: dump the instruction execution size
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2017-01-03 Iago Toral Quirogai965/vec4: use the IR's execution size
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2017-01-03 Iago Toral Quirogai965/vec4: fix regs_read() for doubles
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2017-01-03 Iago Toral Quirogai965/vec4: fix size_written for doubles
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2017-01-03 Iago Toral Quirogai965: move exec_size from fs_instruction to backend_instruction
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2017-01-03 Samuel Iglesias... i965/vec4: use the new helper function to create double...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: add a helper function to create double immediates
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Iago Toral Quirogai965/vec4: fix optimize predicate for doubles
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2017-01-03 Iago Toral Quirogai965/vec4: implement fsign() for doubles
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2017-01-03 Iago Toral Quirogai965/vec4: implement d2b
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2017-01-03 Iago Toral Quirogai965/vec4: implement d2i, d2u, i2d and u2d
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2017-01-03 Iago Toral Quirogai965/vec4: implement HW workaround for align16 double...
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2017-01-03 Iago Toral Quirogai965/vec4: add helpers for conversions to/from doubles
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2017-01-03 Iago Toral Quirogai965/vec4: Rename DF to/from F generator opcodes
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2017-01-03 Iago Toral Quirogai965/vec4: fix register allocation for 64-bit undef...
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2017-01-03 Iago Toral Quirogai965/vec4: make opt_vector_float ignore doubles
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2017-01-03 Iago Toral Quirogai965/vec4: fix get_nir_dest() to use DF type for 64...
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2017-01-03 Iago Toral Quirogai965/vec4: fix indentation in get_nir_src()
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2017-01-03 Iago Toral Quirogai965/vec4/nir: implement double comparisons
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2017-01-03 Iago Toral Quirogai965/vec4: implement double packing
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2017-01-03 Iago Toral Quirogai965/vec4: implement double unpacking
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2017-01-03 Iago Toral Quirogai965/vec4: don't copy propagate vector opcodes that...
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2017-01-03 Iago Toral Quirogai965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
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2017-01-03 Iago Toral Quirogai965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
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2017-01-03 Iago Toral Quirogai965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
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2017-01-03 Iago Toral Quirogai965/vec4: add dst_null_df()
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2017-01-03 Iago Toral Quirogai965/vec4: We only support 32-bit integer ALU operations...
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2017-01-03 Iago Toral Quirogai965/disasm: align16 DF source regions have a width...
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2017-01-03 Iago Toral Quirogai965/vec4: set correct register regions for 32-bit...
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2017-01-03 Connor Abbotti965: add brw_vecn_grf()
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2017-01-03 Iago Toral Quirogai965/vec4: translate d2f/f2d
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2017-01-03 Iago Toral Quirogai965/vec4: add double/float conversion pseudo-opcodes
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2017-01-03 Connor Abbotti965/vec4: add support for printing DF immediates
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2017-01-03 Iago Toral Quirogai965/vec4/nir: fix emitting 64-bit immediates
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2017-01-03 Connor Abbotti965/vec4/nir: set the right type for 64-bit registers
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2017-01-03 Iago Toral Quirogai965/vec4/nir: support doubles in ALU operations
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2017-01-03 Iago Toral Quirogai965/vec4/nir: Add bit-size information to types
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2017-01-03 Connor Abbotti965/vec4/nir: allocate two registers for dvec3/dvec4
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2017-01-03 Connor Abbotti965/vec4/nir: simplify glsl_type_for_nir_alu_type()
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2017-01-03 Samuel Iglesias... i965/nir: double/dvec2 uniforms only need to be padded...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2017-01-03 Samuel Iglesias... i965/fs: fix exec_size when emitting DIM instruction
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-11-15 Samuel Iglesias... main: return error if asking for GL_TEXTURE_BORDER_COLOR...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-10-26 Samuel Iglesias... glsl: update default precision qualifier when it is...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-10-26 Samuel Iglesias... mesa/program: Add _mesa_symbol_table_replace_symbol()
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-10-24 Samuel Iglesias... glsl/es31: precision qualifier doesn't need to match...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-10-24 Samuel Iglesias... glsl: move intrastage_match() after interstage_member_mismatch()
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-07-14 Samuel Iglesias... i965/fs: emit DIM instruction to load 64-bit immediates...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-07-14 Samuel Iglesias... i965/eu: set DF imm value to the source of DIM
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-07-14 Samuel Iglesias... i965: enable the emission of the DIM instruction
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-07-13 Samuel Iglesias... i965/fs: do d2x lowering before simd splitting
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-07-13 Iago Toral Quirogai965/fs: do pack lowering before simd splitting
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2016-07-13 Samuel Iglesias... i965/fs: do not require force_writemask_all with exec_size 4
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2016-07-13 Iago Toral Quirogai965/fs/gen7: split instructions that run into exec...
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2016-07-13 Iago Toral Quirogai965/fs: use the new helper function to create double...
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2016-07-13 Iago Toral Quirogai965/fs: add a helper function to create double immediates
 ...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-06-17 Samuel Iglesias... i965/fs: indirect addressing with doubles is not supported...
...by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
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2016-06-17 Iago Toral Quirogai965/fs: Fix single-precision to double-precision conversion...
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