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Remove leftover comment
2019-04-11
Eddie Hung
Fix ordering of when to insert zero index
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tree
2019-04-11
Eddie Hung
More unused
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2019-04-11
Eddie Hung
Remove unused
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2019-04-11
Eddie Hung
Fixes
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tree
2019-04-11
Eddie Hung
WIP
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tree
2019-04-11
Eddie Hung
Spelling fixes
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tree
2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases covered...
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2019-04-10
Eddie Hung
synth_* with -retime option now calls abc with -D 1...
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2019-04-10
Eddie Hung
Revert "abc -dff now implies "-D 0" otherwise retiming...
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2019-04-10
Eddie Hung
Revert ""&nf -D 0" fails => use "-D 1" instead"
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2019-04-10
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-04-08
Eddie Hung
Fix a few typos
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2019-04-08
Eddie Hung
$_XILINX_SHREG_ to preserve src attribute
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2019-04-08
Eddie Hung
Update CHANGELOG
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2019-04-08
Eddie Hung
Merge branch 'undo_pr895' into xc7srl
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2019-04-08
Eddie Hung
Undo #895 by instead setting an attribute
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2019-04-08
Eddie Hung
Cope with undoing #895
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2019-04-08
Eddie Hung
Revert "Remove handling for $pmux, since #895"
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2019-04-06
Eddie Hung
Call shregmap twice -- once for variable, another for...
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Add retime test
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2019-04-05
Eddie Hung
Fix S0 -> S1
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2019-04-05
Eddie Hung
Move dffinit til after abc
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Move techamp t:$_DFF_?N? to before abc call
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2019-04-05
Eddie Hung
Retry
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2019-04-05
Eddie Hung
"&nf -D 0" fails => use "-D 1" instead
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2019-04-05
Eddie Hung
Resolve @daveshah1 comment, update synth_xilinx help
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2019-04-05
Eddie Hung
synth_xilinx to techmap FFs after abc call, otherwise...
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2019-04-05
Eddie Hung
abc -dff now implies "-D 0" otherwise retiming doesn...
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2019-04-05
Eddie Hung
techmap inside map_cells stage
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
Missing techmap entry in help
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2019-04-04
Eddie Hung
Use soft-logic, not LUT3 instantiation
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2019-04-04
Eddie Hung
Merge branch 'map_cells_before_map_luts' into xc7srl
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2019-04-04
Eddie Hung
synth_xilinx to map_cells before map_luts
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2019-04-04
Eddie Hung
Cleanup comments
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2019-04-04
Eddie Hung
t:$dff* -> t:$dff t:$dffe
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2019-04-03
Eddie Hung
Remove handling for $pmux, since #895
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2019-04-03
Eddie Hung
-nosrl meant when -nobram
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2019-04-03
Eddie Hung
Remove duplicate STARTUPE2
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2019-04-03
Eddie Hung
Disable shregmap in synth_xilinx if -retime
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2019-04-03
Eddie Hung
Add changelog entry
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2019-04-03
Eddie Hung
Merge pull request #913 from smunaut/fix_proc_mux
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-03-25
Eddie Hung
synth_xilinx to use shregmap with -minlen 3
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2019-03-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-23
Eddie Hung
Add a pmux-to-shiftx optimisation to proc_mux
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2019-03-23
Eddie Hung
Cope with SHREG not having E port; Revert $pmux fine...
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2019-03-23
Eddie Hung
Add support for SHREGMAP+$mux, also fine tune $pmux
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2019-03-23
Eddie Hung
Leftover printf
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2019-03-23
Eddie Hung
Fixes for multibit
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2019-03-23
Eddie Hung
Working for 1 bit
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2019-03-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-21
Eddie Hung
Add '-nosrl' option to synth_xilinx
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2019-03-21
Eddie Hung
Opt
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tree
2019-03-20
Eddie Hung
Fix spacing
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2019-03-20
Eddie Hung
Fine tune cells_map.v
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2019-03-20
Eddie Hung
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable...
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2019-03-20
Eddie Hung
Add support for variable length Xilinx SRL > 128
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2019-03-19
Eddie Hung
Restore original synth_xilinx commands
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2019-03-19
Eddie Hung
Fix spacing
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2019-03-19
Eddie Hung
shregmap -tech xilinx to delete $shiftx for var length SRL
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2019-03-19
Eddie Hung
Fix INIT for variable length SRs that have been bumped...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Make output port a non chain user
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2019-03-19
Eddie Hung
Merge pull request #808 from eddiehung/read_aiger
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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tree
2019-03-19
Eddie Hung
Add author name
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2019-03-18
Eddie Hung
Fix shregmap to correctly recognise non chain users...
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2019-03-18
Eddie Hung
shiftx NULL pointer check
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2019-03-16
Eddie Hung
Cleanup
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2019-03-16
Eddie Hung
Only accept <128 for variable length, only if $shiftx...
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2019-03-16
Eddie Hung
Cleanup synth_xilinx
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2019-03-16
Eddie Hung
Working
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2019-03-14
Eddie Hung
Reverse bits in INIT parameter for Xilinx, since MSB...
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2019-03-14
Eddie Hung
Misspell
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2019-03-14
Eddie Hung
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14
Eddie Hung
Add shregmap -init_msb_first and use in synth_xilinx
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2019-03-14
Eddie Hung
Fix cells_map for SRL
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2019-03-14
Eddie Hung
Move shregmap until after first techmap
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2019-03-13
Eddie Hung
Refactor $__SHREG__ in cells_map.v
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2019-03-11
Eddie Hung
Merge pull request #864 from YosysHQ/svalabelfix
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2019-03-09
Eddie Hung
Update help message for -chparam
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2019-03-09
Eddie Hung
Add -chparam option to verific command
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2019-03-09
Eddie Hung
Fix spelling
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2019-03-06
Eddie Hung
Fix spelling in pmgen/README.md
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2019-02-28
Eddie Hung
Remove SRL16/32 from cells_xtra
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2019-02-28
Eddie Hung
Add SRL16 and SRL32 sim models
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2019-02-28
Eddie Hung
Fix SRL16/32 techmap off-by-one
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2019-02-28
Eddie Hung
synth_xilinx to call shregmap with enable support
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2019-02-28
Eddie Hung
synth_xilinx to use shregmap with -params too
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2019-02-28
Eddie Hung
synth_xilinx to now have shregmap call after dff2dffe
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2019-02-28
Eddie Hung
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
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2019-02-21
Eddie Hung
Revert "Add -B option to autotest.sh to append to backend_opts"
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2019-02-21
Eddie Hung
Merge pull request #817 from eddiehung/dff_init
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