git.libre-soc.org Git - nmigen.git/search

2020-05-22	whitequark	back.verilog: fall back to nmigen_yosys package.	commit \| commitdiff \| tree
2020-05-21	whitequark	Update .gitignore.	commit \| commitdiff \| tree
2020-05-21	whitequark	vendor.intel: don't use `write_verilog -decimal`.	commit \| commitdiff \| tree
2020-05-21	whitequark	vendor.intel: double-quote Tcl values rather than brace...	commit \| commitdiff \| tree
2020-05-21	whitequark	vendor.xilinx_{7series,ultrascale}: don't use `write_verilog...	commit \| commitdiff \| tree
2020-05-20	whitequark	build.plat: skip clock constraints on unused signals.	commit \| commitdiff \| tree
2020-05-20	whitequark	vendor.xilinx_{7series,ultrascale}: add (keep) on...	commit \| commitdiff \| tree
2020-05-20	whitequark	hdl.ast: add const-shift operations.	commit \| commitdiff \| tree
2020-05-19	whitequark	hdl.ast: clarify docs for Value.rotate_{left,right}.	commit \| commitdiff \| tree
2020-05-19	whitequark	hdl.dsl: check for unique domain name.	commit \| commitdiff \| tree
2020-05-19	whitequark	back.rtlil: handle signed and large Instance parameters...	commit \| commitdiff \| tree
2020-05-17	whitequark	tracer: fix get_var_name() to work on toplevel attributes.	commit \| commitdiff \| tree
2020-05-02	whitequark	plat, vendor: systematically escape net and file names...	commit \| commitdiff \| tree
2020-04-28	whitequark	back.rtlil: fix incorrect escaping of signed parameters.	commit \| commitdiff \| tree
2020-04-27	whitequark	hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signals().	commit \| commitdiff \| tree
2020-04-27	whitequark	lib.cdc: add missing documentation for AsyncFFSynchronizer...	commit \| commitdiff \| tree
2020-04-24	whitequark	README: link directly to Yosys build instructions.	commit \| commitdiff \| tree
2020-04-15	whitequark	back.rtlil: translate enum decoders to Yosys enum attributes.	commit \| commitdiff \| tree
2020-04-14	whitequark	buil.plat: enable strict undefined behavior in Jinja2.	commit \| commitdiff \| tree
2020-04-13	whitequark	back.rtlil: don't emit connections to zero width ports.	commit \| commitdiff \| tree
2020-04-13	whitequark	back.rtlil: refuse to create extremely large wires.	commit \| commitdiff \| tree
2020-04-13	whitequark	back.rtlil: fix expansion of Part() for partial dummy...	commit \| commitdiff \| tree
2020-04-13	whitequark	back.rtlil: fix legalization of Part() with stride.	commit \| commitdiff \| tree
2020-04-13	whitequark	Clarify a few comments. NFC.	commit \| commitdiff \| tree
2020-04-13	whitequark	Travis: require tests to pass on pypy3.	commit \| commitdiff \| tree
2020-04-13	whitequark	Travis: upgrade to bionic.	commit \| commitdiff \| tree
2020-04-12	whitequark	build.run: fix BuildProducts.extract to work with subdirecto...	commit \| commitdiff \| tree
2020-04-12	whitequark	hdl.rec: improve repr() for Layout.	commit \| commitdiff \| tree
2020-04-12	whitequark	hdl.ast: improve repr() for Shape.	commit \| commitdiff \| tree
2020-04-12	whitequark	build.plat: don't check for toolchain presence if do_build...	commit \| commitdiff \| tree
2020-04-05	whitequark	hdl.mem: fix source location of ReadPort.en.	commit \| commitdiff \| tree
2020-04-03	whitequark	back.pysim: fix emission of undriven traces to VCD...	commit \| commitdiff \| tree
2020-04-02	whitequark	setup: bump pyvcd to ~=0.2.	commit \| commitdiff \| tree
2020-04-02	whitequark	setup: tighten version constraint on Jinja2.	commit \| commitdiff \| tree
2020-03-22	whitequark	hdl.ast: implement abs() on values.	commit \| commitdiff \| tree
2020-03-12	whitequark	vendor: fix a few issues in commit 2f8669ca.	commit \| commitdiff \| tree
2020-02-19	whitequark	hdl.ast: fix off-by-1 in Initial.__init__().	commit \| commitdiff \| tree
2020-02-19	whitequark	back.pysim: fix RHS codegen for Cat() and Repl(......	commit \| commitdiff \| tree
2020-02-19	whitequark	back.pysim: optionally allow introspecting generated...	commit \| commitdiff \| tree
2020-02-14	whitequark	Travis: prune dependencies.	commit \| commitdiff \| tree
2020-02-14	whitequark	Travis: test on Python 3.8.	commit \| commitdiff \| tree
2020-02-12	whitequark	cli: update use of deprecated code.	commit \| commitdiff \| tree
2020-02-12	whitequark	back.pysim: accept write_vcd(vcd_file=None).	commit \| commitdiff \| tree
2020-02-09	whitequark	setup: update project URLs.	commit \| commitdiff \| tree
2020-02-09	whitequark	doc: remove outdated files and references to them.	commit \| commitdiff \| tree
2020-02-08	whitequark	README: link to IRC channel.	commit \| commitdiff \| tree
2020-02-08	whitequark	README: consolidate requirements in the Installation...	commit \| commitdiff \| tree
2020-02-07	whitequark	test_build_res: fix after commit 3e2ecdf2.	commit \| commitdiff \| tree
2020-02-06	whitequark	build.res,vendor: place clock constraint on port, not...	commit \| commitdiff \| tree
2020-02-06	whitequark	xilinx_{7series,ultrascale}: run `report_methodology`.	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.ast: add Value.{as_signed,as_unsigned}.	commit \| commitdiff \| tree
2020-02-06	whitequark	test_lib_fifo: define all referenced FSM states.	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.dsl: make referencing undefined FSM states an error.	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.ir: type check ports.	commit \| commitdiff \| tree
2020-02-06	whitequark	back.pysim: emit toplevel inputs in VCD files as well.	commit \| commitdiff \| tree
2020-02-06	whitequark	back.pysim: make `write_vcd(traces=)` actually use...	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.dsl: reject name mismatch in `m.domains.<name>...	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.dsl: type check when adding to m.domains.	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.mem: add synthesis attribute support.	commit \| commitdiff \| tree
2020-02-06	whitequark	hdl.mem: document Memory.	commit \| commitdiff \| tree
2020-02-04	whitequark	hdl.{ast,dsl}: allow whitespace in bit patterns.	commit \| commitdiff \| tree
2020-02-01	whitequark	hdl.ast: update documentation for Signal.	commit \| commitdiff \| tree
2020-02-01	whitequark	hdl.ast: prohibit shifts by signed value.	commit \| commitdiff \| tree
2020-02-01	whitequark	build.plat: align pipeline with Fragment.prepare().	commit \| commitdiff \| tree
2020-02-01	whitequark	hdl.dsl: don't allow inheriting from Module.	commit \| commitdiff \| tree
2020-02-01	whitequark	hdl.ast: warn on unused property statements (Assert...	commit \| commitdiff \| tree
2020-02-01	whitequark	_unused: extract must-use logic from hdl.ir.	commit \| commitdiff \| tree
2020-01-31	whitequark	hdl.dsl: add missing case width check for Enum values.	commit \| commitdiff \| tree
2020-01-31	whitequark	README: clarify relationship to Migen.	commit \| commitdiff \| tree
2020-01-31	whitequark	hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error.	commit \| commitdiff \| tree
2020-01-31	whitequark	back.rtlil: don't emit wires for empty signals.	commit \| commitdiff \| tree
2020-01-27	whitequark	Update README.	commit \| commitdiff \| tree
2020-01-18	whitequark	hdl.ir: resolve hierarchy conflicts before creating...	commit \| commitdiff \| tree
2020-01-17	whitequark	hdl.xfrm: transform drivers as well in DomainRenamer.	commit \| commitdiff \| tree
2020-01-12	whitequark	Remove everything deprecated in nmigen 0.1.	commit \| commitdiff \| tree
2020-01-01	whitequark	back.rtlil: do not consider unreachable array elements...	commit \| commitdiff \| tree
2019-12-15	whitequark	hdl.mem: fix src_loc_at in ReadPort, WritePort.	commit \| commitdiff \| tree
2019-12-02	whitequark	back.pysim: fix miscompilation of Signal(unsigned)...	commit \| commitdiff \| tree
2019-12-02	whitequark	hdl.ast: actually remove simulator commands.	commit \| commitdiff \| tree
2019-11-28	whitequark	back.pysim: redesign the simulator.	commit \| commitdiff \| tree
2019-11-27	whitequark	back.rtlil: infer bit width for instance parameters.	commit \| commitdiff \| tree
2019-11-26	whitequark	hdl.ir: for instance ports, prioritize defs over uses.	commit \| commitdiff \| tree
2019-11-18	whitequark	back.rtlil: extend shorter operand of a binop when...	commit \| commitdiff \| tree
2019-11-15	whitequark	build.plat: in Platform.add_file(), allow adding exact...	commit \| commitdiff \| tree
2019-11-15	whitequark	test: add tests for build.plat.Platform.add_file.	commit \| commitdiff \| tree
2019-11-09	whitequark	hdl.rec: fix Record.like() being called through a subclass.	commit \| commitdiff \| tree
2019-11-07	whitequark	hdl.ir: lower domains before resolving hierarchy conflicts.	commit \| commitdiff \| tree
2019-11-02	whitequark	Improve .gitignore.	commit \| commitdiff \| tree
2019-10-28	whitequark	back.verilog: remove $verilog_initial_trigger after...	commit \| commitdiff \| tree
2019-10-26	whitequark	test: use `#nmigen:` magic comment instead of monkey...	commit \| commitdiff \| tree
2019-10-26	whitequark	hdl.ir: allow disabling UnusedElaboratable warning...	commit \| commitdiff \| tree
2019-10-26	whitequark	back.rtlil: avoid exponential behavior when legalizing...	commit \| commitdiff \| tree
2019-10-26	whitequark	back.rtlil: fix lowering of Part() on LHS to account...	commit \| commitdiff \| tree
2019-10-26	whitequark	hdl.ast: simplify {bit,word}_select with constant offset.	commit \| commitdiff \| tree
2019-10-21	whitequark	Explicitly restrict prelude imports.	commit \| commitdiff \| tree
2019-10-17	whitequark	compat.fhdl.specials: fix argument parsing compatibility.	commit \| commitdiff \| tree
2019-10-16	whitequark	lib.io: use keyword-only arguments in Pin().	commit \| commitdiff \| tree
2019-10-16	whitequark	setup: fix commit 5198d99b.	commit \| commitdiff \| tree
2019-10-16	whitequark	back.verilog: fix Yosys version check.	commit \| commitdiff \| tree
2019-10-15	whitequark	setup: don't append local version for tags.	commit \| commitdiff \| tree
next

RSS Atom