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add cs_latch as a peer of bus_latch in case the address changes
2022-03-28
Luke Kenneth Casson...
add cs_latch as a peer of bus_latch in case the address...
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2022-03-28
Luke Kenneth Casson...
minor simplification of hyperram: using constants
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2022-03-28
Luke Kenneth Casson...
extend cs in hyperram to multiple bits
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2022-03-27
Luke Kenneth Casson...
update code-comments
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2022-03-27
Luke Kenneth Casson...
add reset pad to hyperram, should be set externally
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2022-03-26
Luke Kenneth Casson...
hyperram CS inverted (corrected)
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2022-03-26
Luke Kenneth Casson...
sort out hyperram ports down to test class
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2022-03-25
Luke Kenneth Casson...
fix attributes, sort out address
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2022-03-19
Luke Kenneth Casson...
rename hyperram clk pads to "ck"
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2022-03-18
Luke Kenneth Casson...
cleanup
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2022-03-18
Luke Kenneth Casson...
add ports function to HyperRAMPHY
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2022-03-18
Luke Kenneth Casson...
rename TestHyperRAMPHY to just HyperRAMPHY
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2022-03-18
Luke Kenneth Casson...
move HyperRAMPads and Test PHY to hyperram.py module
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2022-03-18
Luke Kenneth Casson...
remove redundant implementation of migen "timeline"
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2022-03-18
Luke Kenneth Casson...
document useful "add_extension" for HyperRAM PMODs
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2022-03-16
Luke Kenneth Casson...
update HyperRAM module and add unit test
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2022-03-15
Luke Kenneth Casson...
add first version of hyperram.py
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