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Try new LUT delays
2019-05-25
Eddie Hung
Try new LUT delays
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2019-05-24
Eddie Hung
Add &fraig and &mfs back
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2019-05-24
Eddie Hung
Transpose CARRY4 delays
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/opt_rmdff...
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2019-05-23
Eddie Hung
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
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2019-05-23
Eddie Hung
Fix spacing
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2019-05-23
Eddie Hung
Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23
Eddie Hung
Add opt_rmdff tests
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2019-05-23
Eddie Hung
opt_rmdff to work on $dffe and $_DFFE_*
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2019-05-23
Eddie Hung
Add whitebox support to DRAM
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2019-05-22
Eddie Hung
shift register inference before mux
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2019-05-22
Eddie Hung
Fix/workaround symptom unveiled by #1023
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2019-05-22
Eddie Hung
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces
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2019-05-22
Eddie Hung
Rename label
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2019-05-22
Eddie Hung
Try again
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2019-05-21
Eddie Hung
Fix warning
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2019-05-21
Eddie Hung
Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21
Eddie Hung
Pad all boxes so that all input/output connections...
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2019-05-21
Eddie Hung
Modify LUT area cost to be same as old abc
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-03
Eddie Hung
More testing
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2019-05-03
Eddie Hung
Fix spacing
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2019-05-03
Eddie Hung
Add quick-and-dirty specify tests
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into clifford...
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2019-05-03
Eddie Hung
Rename cells_map.v to prevent clash with ff_map.v
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2019-05-03
Eddie Hung
iverilog with simcells.v as well
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2019-05-03
Eddie Hung
log_warning_noprefix -> log_warning as per review
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2019-05-03
Eddie Hung
For hier_tree::Elaborate() also include SV root modules...
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2019-05-03
Eddie Hung
Fix verific_parameters construction, use attribute...
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2019-05-03
Eddie Hung
WIP -chparam support for hierarchy when verific
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2019-05-03
Eddie Hung
verific_import() changes to avoid ElaborateAll()
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2019-05-03
Eddie Hung
Revert "synth_xilinx to call dffinit with -noreinit"
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2019-05-03
Eddie Hung
If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03
Eddie Hung
Revert "dffinit -noreinit to silently continue when...
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2019-05-03
Eddie Hung
synth_xilinx to call dffinit with -noreinit
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2019-05-03
Eddie Hung
dffinit -noreinit to silently continue when init value...
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2019-05-02
Eddie Hung
Trim off leading 1'bx in A
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2019-05-02
Eddie Hung
Add don't care optimisation
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2019-05-02
Eddie Hung
Use new peepopt from #969
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmgenstuff...
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2019-05-02
Eddie Hung
Revert to pre-muxcover approach
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2019-05-02
Eddie Hung
Missing help_mode
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2019-05-02
Eddie Hung
Fix -nocarry
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-02
Eddie Hung
Merge pull request #978 from ucb-bar/fmtfirrtl
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2019-05-02
Eddie Hung
Back to passing all xc7srl tests!
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2019-05-02
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-05-01
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-04-28
Eddie Hung
Copy with 1'bx padding in $shiftx
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2019-04-28
Eddie Hung
WIP
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2019-04-28
Eddie Hung
Move neg-pol to pos-pol mapping from ff_map to cells_map.v
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2019-04-27
Eddie Hung
Fix spacing
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2019-04-27
Eddie Hung
Remove split_shiftx tests
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2019-04-26
Eddie Hung
Revert synth_xilinx 'fine' label more to how it used...
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2019-04-26
Eddie Hung
Apparently, this reduces number of MUXCY/XORCY
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2019-04-26
Eddie Hung
Try a different approach with 'muxcover'
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2019-04-26
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-26
Eddie Hung
Where did this check come from!?!
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2019-04-26
Eddie Hung
Remove split_shiftx call
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2019-04-26
Eddie Hung
Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
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2019-04-26
Eddie Hung
Missing newline
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2019-04-26
Eddie Hung
Refactor synth_xilinx to auto-generate doc
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2019-04-26
Eddie Hung
Cleanup ice40
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2019-04-26
Eddie Hung
Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-26
Eddie Hung
Add -undef option to equiv_opt, passed to equiv_induct
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2019-04-26
Eddie Hung
Actually use pm.st.shiftxB
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2019-04-26
Eddie Hung
Cleanup superseded
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2019-04-26
Eddie Hung
bitblast_shiftx -> split_shiftx
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2019-04-26
Eddie Hung
Fix for when B_WIDTH has trailing zeroes
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2019-04-26
Eddie Hung
Merge remote-tracking branch 'origin/eddie/split_shiftx...
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2019-04-26
Eddie Hung
In order to indicate a failed pattern, blacklist?
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2019-04-26
Eddie Hung
Add test
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2019-04-26
Eddie Hung
Elaborate on help message
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2019-04-26
Eddie Hung
Merge branch 'eddie/split_shiftx' into xc7mux
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2019-04-26
Eddie Hung
Add split_shiftx command
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2019-04-26
Eddie Hung
Make pmgen support files more generic
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2019-04-26
Eddie Hung
synth_xilinx to call bitblast_shiftx
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2019-04-25
Eddie Hung
Misspelling
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2019-04-25
Eddie Hung
Remove topo sort no-loop assertion, with test
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2019-04-24
Eddie Hung
Add -nocarry option to synth_xilinx
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2019-04-23
Eddie Hung
Fix abc9 with (* keep *) wires
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2019-04-23
Eddie Hung
Refactor into AigerReader::post_process()
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2019-04-23
Eddie Hung
Format some names using inline code
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2019-04-23
Eddie Hung
Fix spelling
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2019-04-23
Eddie Hung
Tweak
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2019-04-23
Eddie Hung
Fix for A_WIDTH == 2 but B_WIDTH==3
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2019-04-23
Eddie Hung
Trim A_WIDTH by Y_WIDTH-1
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2019-04-22
Eddie Hung
Add comment
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2019-04-22
Eddie Hung
Fix for mux_case_* mappings
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2019-04-22
Eddie Hung
Fix for non-pow2 width muxes
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2019-04-22
Eddie Hung
Merge pull request #914 from YosysHQ/xc7srl
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2019-04-22
Eddie Hung
Add synth_xilinx -nomux option
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2019-04-22
Eddie Hung
Cleanup, call pmux2shiftx even without -nosrl
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2019-04-22
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-22
Eddie Hung
Temporarily remove 'r' extension
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2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
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2019-04-22
Eddie Hung
Update help message
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2019-04-22
Eddie Hung
Allow POs to be PIs in XAIG
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2019-04-22
Eddie Hung
Remove kernel/cost.cc since master has refactored it
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