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Rename memory tests to lutram, add more xilinx tests
2019-12-13
Eddie Hung
Rename memory tests to lutram, add more xilinx tests
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2019-12-12
Eddie Hung
abc9_map.v: fix Xilinx LUTRAM
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2019-12-12
Eddie Hung
Update README.md :: abc_ -> abc9_
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2019-12-11
Eddie Hung
Fix bitwidth mismatch; suppresses iverilog warning
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2019-12-10
Eddie Hung
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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2019-12-09
Eddie Hung
ice40_opt to restore attributes/name when unwrapping
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2019-12-09
Eddie Hung
ice40_wrapcarry -unwrap to preserve 'src' attribute
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2019-12-09
Eddie Hung
unmap $__ICE40_CARRY_WRAPPER in test
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2019-12-09
Eddie Hung
-unwrap to create $lut not SB_LUT4 for opt_lut
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2019-12-09
Eddie Hung
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER...
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2019-12-09
Eddie Hung
ice40_wrapcarry to really preserve attributes via ...
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2019-12-07
Eddie Hung
Merge pull request #1555 from antmicro/fix-macc-xilinx...
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2019-12-07
Eddie Hung
Drop keep=0 attributes on SB_CARRY
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2019-12-05
Eddie Hung
Merge SB_CARRY+SB_LUT4's attributes when creating ...
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2019-12-05
Eddie Hung
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
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2019-12-03
Eddie Hung
Check SB_CARRY name also preserved
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2019-12-03
Eddie Hung
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for...
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2019-12-03
Eddie Hung
ice40_opt to ignore (* keep *) -ed cells
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2019-12-03
Eddie Hung
ice40_wrapcarry to preserve SB_CARRY's attributes
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2019-12-03
Eddie Hung
Add testcase
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2019-11-28
Eddie Hung
Revert "Fold loop"
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2019-11-27
Eddie Hung
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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2019-11-27
Eddie Hung
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
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2019-11-27
Eddie Hung
No need for -abc9
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2019-11-27
Eddie Hung
latch -> box
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2019-11-27
Eddie Hung
Add citation
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2019-11-27
Eddie Hung
Check for either sign or zero extension for postAdd...
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2019-11-27
Eddie Hung
Remove notes
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2019-11-27
Eddie Hung
Fold loop
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2019-11-27
Eddie Hung
Do not sigmap keep bits inside write_xaiger
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2019-11-27
Eddie Hung
xaiger: do not promote output wires
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2019-11-27
Eddie Hung
Add testcase derived from fastfir_dynamictaps benchmark
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2019-11-23
Eddie Hung
Merge pull request #1520 from pietrmar/fix-1463
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2019-10-17
Eddie Hung
Add -assert
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2019-10-17
Eddie Hung
Use built-in async2sync call as per #1417
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2019-10-17
Eddie Hung
Update mul test to DSP48E1
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2019-10-17
Eddie Hung
Update area for div_mod
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2019-10-17
Eddie Hung
Add comment for lack of tristate logic pointing to...
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2019-10-17
Eddie Hung
Move $x to end as 7f0eec8
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2019-10-08
Eddie Hung
Revert "Add test that is expecting to fail"
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2019-10-08
Eddie Hung
Revert "Be mindful that sigmap(wire) could have dupes...
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2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
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2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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2019-10-08
Eddie Hung
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
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2019-10-05
Eddie Hung
Missing 'accept' at end of ice40_wrapcarry, spotted...
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2019-10-05
Eddie Hung
Missed this
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2019-10-05
Eddie Hung
Add comment on why we have to match for clock-enable...
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2019-10-05
Eddie Hung
Add note on pattern detector
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2019-10-05
Eddie Hung
Add comment on why partial multipliers are 18x18
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp_cascade
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2019-10-05
Eddie Hung
Improve comments for xilinx_dsp_CREG
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2019-10-05
Eddie Hung
Fix comment
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2019-10-05
Eddie Hung
Restore optimisation for sigM.empty()
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2019-10-05
Eddie Hung
Retry on fixing TODOs
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2019-10-05
Eddie Hung
Revert "Fix TODOs"
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2019-10-05
Eddie Hung
More comments, cleanup
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2019-10-05
Eddie Hung
Fix TODOs
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2019-10-05
Eddie Hung
Consistency
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2019-10-05
Eddie Hung
Add comments for xilinx_dsp
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2019-10-05
Eddie Hung
Fix typo in check_label()
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Add temporary `abc9 -nomfs` and use for `synth_xilinx...
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2019-10-05
Eddie Hung
Remove DSP48E1 from *_cells_xtra.v
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2019-10-04
Eddie Hung
Fix xilinx_dsp for unsigned extensions
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2019-10-04
Eddie Hung
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true...
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2019-10-04
Eddie Hung
Add Const::{begin,end,empty}()
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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2019-10-04
Eddie Hung
Panic over. Model was elsewhere. Re-arrange for consistency
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2019-10-04
Eddie Hung
Oops
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2019-10-04
Eddie Hung
Ohmilord this wasn't added all this time!?!
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2019-10-04
Eddie Hung
Add -async2sync to help text as per @daveshah1
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2019-10-03
Eddie Hung
Use `sat -tempinduct` and comments for why equiv_opt...
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2019-10-03
Eddie Hung
Restore part of doc
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2019-10-03
Eddie Hung
Disable equiv check for ice40 latches
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2019-10-03
Eddie Hung
Add new -async2sync option
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2019-10-03
Eddie Hung
Use equiv_opt -async2sync for xilinx
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2019-10-03
Eddie Hung
Revert "equiv_opt to call async2sync when not -multiclock...
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2019-10-03
Eddie Hung
Revert "Update doc for equiv_opt"
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2019-10-03
Eddie Hung
Fix broken CI, check reset even for constants, trim...
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2019-10-03
Eddie Hung
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
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2019-10-03
Eddie Hung
Fix test
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2019-10-03
Eddie Hung
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
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2019-10-03
Eddie Hung
Update test
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2019-10-03
Eddie Hung
Refactor peepopt_dffmux and be sensitive to \init when...
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2019-10-03
Eddie Hung
Add test
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2019-10-03
Eddie Hung
log_dump() to support State enum
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2019-10-02
Eddie Hung
Be mindful that sigmap(wire) could have dupes when...
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2019-10-02
Eddie Hung
Add test that is expecting to fail
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2019-10-02
Eddie Hung
Also rename cells with _TECHMAP_REPLACE_. prefix, as...
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2019-10-02
Eddie Hung
Extend test with renaming cells with prefix too
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2019-10-01
Eddie Hung
equiv_opt with -assert
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2019-10-01
Eddie Hung
Update resource count for alu.ys
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2019-10-01
Eddie Hung
Add test
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2019-10-01
Eddie Hung
techmap wires named _TECHMAP_REPLACE_.<identifier>...
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2019-09-30
Eddie Hung
Add quick test
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2019-09-30
Eddie Hung
Add -select option to aigmap
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2019-09-30
Eddie Hung
Fix typo
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2019-09-30
Eddie Hung
Move $x to end as per 7f0eec8
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2019-09-30
Eddie Hung
Update fsm.ys resource count
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