2021-09-03 |
Luke Kenneth Casson... | another batch of ready/valid i/o prefix-suffix swaps
|
commit | commitdiff | tree |
2021-08-31 |
Luke Kenneth Casson... | anooother valid_o to convert to o_valid
|
commit | commitdiff | tree |
2021-08-31 |
Luke Kenneth Casson... | update ready/valid in shift_rot test_pipe_caller
|
commit | commitdiff | tree |
2021-08-30 |
Luke Kenneth Casson... | update ready/valid i/o_ prefix in div test helper.py
|
commit | commitdiff | tree |
2021-08-30 |
Luke Kenneth Casson... | fix ready/valid i/o prefix in ALU test
|
commit | commitdiff | tree |
2021-08-30 |
Luke Kenneth Casson... | fix CR tests valid/ready naming
|
commit | commitdiff | tree |
2021-08-30 |
Luke Kenneth Casson... | missed valid/ready_i/o to o/i_ conversion
|
commit | commitdiff | tree |
2021-08-30 |
Luke Kenneth Casson... | missed valid/ready_i/o to o/i_ conversion
|
commit | commitdiff | tree |
2021-08-29 |
Luke Kenneth Casson... | unnecessary signal rename ivalid_i to ii_valid (reverting)
|
commit | commitdiff | tree |
2021-08-24 |
Luke Kenneth Casson... | replace data_o with o_data and data_i with i_data as...
|
commit | commitdiff | tree |
2021-08-24 |
Luke Kenneth Casson... | big rename, global/search/replace of ready_o with o_ready...
|
commit | commitdiff | tree |
2021-08-22 |
Luke Kenneth Casson... | remove svanalysis from Makefile, it is now part of...
|
commit | commitdiff | tree |
2021-08-01 |
Luke Kenneth Casson... | move unused directory out of src, to indicate "ignore...
|
commit | commitdiff | tree |
2021-08-01 |
Luke Kenneth Casson... | simulator/test_sim.py should not have been added
|
commit | commitdiff | tree |
2021-07-15 |
Luke Kenneth Casson... | update TestRunner, SVSTATE is now a class that inherits...
|
commit | commitdiff | tree |
2021-07-14 |
Luke Kenneth Casson... | update SVSTATE to 64 bit length (fortunately very easy)
|
commit | commitdiff | tree |
2021-07-12 |
Luke Kenneth Casson... | use standard create_pdecode in TestRunner
|
commit | commitdiff | tree |
2021-07-12 |
Luke Kenneth Casson... | use default decoder, do not pass one in.
|
commit | commitdiff | tree |
2021-06-24 |
Luke Kenneth Casson... | propagate new use_svp64_ldst_dec mode through TestCore...
|
commit | commitdiff | tree |
2021-06-24 |
Luke Kenneth Casson... | add an explicit PowerDecoder.is_svp64_mode flag to...
|
commit | commitdiff | tree |
2021-06-10 |
Luke Kenneth Casson... | whoops Popcount datalen too big (wasted bits). reduce
|
commit | commitdiff | tree |
2021-06-09 |
Luke Kenneth Casson... | git submodule update
|
commit | commitdiff | tree |
2021-06-09 |
Luke Kenneth Casson... | disconnect pll clock, connected in peripheral interconnect
|
commit | commitdiff | tree |
2021-06-09 |
Luke Kenneth Casson... | add in/out of ref_clk and pllclk_clk when PLL enabled
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | comment out domains that have already been created
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | no, do not assign clock to clock!
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | rename ref to ref_v in PLL due to ref being a verilog...
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | sort out PLL domains but bypass PLL due to lack of...
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | use DomainRenamer on all sub-components of TestIssuer
|
commit | commitdiff | tree |
2021-06-03 |
Luke Kenneth Casson... | make core_rst a member of TestIssuerInternal
|
commit | commitdiff | tree |
2021-05-27 |
Luke Kenneth Casson... | adjust PLL connections looking for coriolis2 issue
|
commit | commitdiff | tree |
2021-05-27 |
Luke Kenneth Casson... | corrections on spblock ack
|
commit | commitdiff | tree |
2021-05-27 |
Luke Kenneth Casson... | classic wishbone mode: must not do ack if already acked
|
commit | commitdiff | tree |
2021-05-26 |
Luke Kenneth Casson... | arse. PLL test_issuer clk_sel_i accidentally only 1...
|
commit | commitdiff | tree |
2021-05-26 |
Luke Kenneth Casson... | remove err feature from sram4k wb
|
commit | commitdiff | tree |
2021-05-26 |
Luke Kenneth Casson... | add ldst PortInterface misalign unit test (underway)
|
commit | commitdiff | tree |
2021-05-26 |
Luke Kenneth Casson... | rename PLL signals
|
commit | commitdiff | tree |
2021-05-24 |
Luke Kenneth Casson... | whoops sort out name of SPBlock RAM
|
commit | commitdiff | tree |
2021-05-24 |
Luke Kenneth Casson... | change name of submodule to real_pll
|
commit | commitdiff | tree |
2021-05-24 |
Luke Kenneth Casson... | match up PLL names
|
commit | commitdiff | tree |
2021-05-22 |
Luke Kenneth Casson... | update submodule
|
commit | commitdiff | tree |
2021-05-22 |
Luke Kenneth Casson... | update PLL to use Instance
|
commit | commitdiff | tree |
2021-05-14 |
Luke Kenneth Casson... | add radix MMU "miss" test
|
commit | commitdiff | tree |
2021-05-14 |
Luke Kenneth Casson... | clear out request data on return to idle
|
commit | commitdiff | tree |
2021-05-14 |
Luke Kenneth Casson... | sort out LoadStore1 misalignment FSM, also required...
|
commit | commitdiff | tree |
2021-05-14 |
Luke Kenneth Casson... | remove minerva units previously missed in cleanout
|
commit | commitdiff | tree |
2021-05-14 |
Luke Kenneth Casson... | add misaligned load through MMU (which is incorrectly...
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | minor rework of wb_get, make generic
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | added STORE test in test_ldst_pi.py, and it worked...
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | update comments in issuer.py regarding a 4th FSM
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | yet more debug log stuff for DCache, this time on CacheRam...
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | fix wb_get error where data was being corrupted
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | add read at different locations in test_ldst_pi.py
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | add some data for MMU to actually look up
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | ha, hilarious: swapped TLBUpdate output sizes db_out...
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | whoops TLBIE must *clear* the valid bit not set it...
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | more debug Display in dcache.py
|
commit | commitdiff | tree |
2021-05-13 |
Luke Kenneth Casson... | putting in a lot more debug print statements in DCache...
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | add dcache tlb / pte test
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | set m_out.load from ldst_r(egister) in LoadStore1
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | move dcache unit test to separate test_dcache.py
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | experimentation with MMU-enabled LoadStore1 through...
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | add debug info, update comments, disable dcache in...
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | start doing virtual memory queries via PortInterface...
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | whoops missing default zero (no idea how)
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | addcomments for MMU PortInterface test (how it, um...
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | bit of a hack to get test_mmu_dcache_pi.py operational.
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
2021-05-12 |
Luke Kenneth Casson... | no need for sel0
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | pass through MSR.PR through PortInterface, into LoadStore1
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | connect MSR.PR to PortInterface in LDSTCompUnit
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | add msr_pr bit in PortInterface
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | add MSR to LD/ST Input Record
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | comment tidyup
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | must also pass through instruction fault exception...
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | whoops names changed in MMU FSM
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | tidyup comments and remove LoadStore COMPLETE state
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | cleanup on exception setting
|
commit | commitdiff | tree |
2021-05-11 |
Luke Kenneth Casson... | rename LoadStore1 data structures back to microwatt...
|
commit | commitdiff | tree |
2021-05-10 |
Luke Kenneth Casson... | add block for MMU activation to LoadStore1
|
commit | commitdiff | tree |
2021-05-10 |
Luke Kenneth Casson... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
|
commit | commitdiff | tree |
2021-05-10 |
Luke Kenneth Casson... | whoops, indentation issue on m.If/m.Else in dcache.py
|
commit | commitdiff | tree |
2021-05-10 |
Luke Kenneth Casson... | add links to set associative image, and bugreport
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add comments on translation of MMU_LOOKUP
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | install MMU_LOOKUP vhdl to be translated to nmigen
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | move (unused) ACK_WAIT code into FSM
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add comments in LoadStore1
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | remove invalid setting of d_in.valid from self.mmureq
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | no SECOND_REQ
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | remove SECOND_REQ
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add comment about LD/ST exception needs copying into...
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | run LD/ST Exception test case for MMU
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add MMU bugtracker link
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | git submodule update
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | update code-comments
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add in alignment exception capture/reporting in LoadStore1
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | preference is to create a temp variable for comb and...
|
commit | commitdiff | tree |
2021-05-09 |
Luke Kenneth Casson... | add misalign flag to PortInterfaceBase
|
commit | commitdiff | tree |
2021-05-08 |
Luke Kenneth Casson... | LoadStore1 tidyup
|
commit | commitdiff | tree |
2021-05-08 |
Luke Kenneth Casson... | transferring more over to LoadStore FSM
|
commit | commitdiff | tree |
next |