2014-08-16 |
Clifford Wolf | Added log_spacer()
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2014-08-15 |
Clifford Wolf | Bugfix in iopadmap
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2014-08-15 |
Clifford Wolf | Renamed $lut ports to follow A-Y naming scheme
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2014-08-15 |
Clifford Wolf | Renamed $_INV_ cell type to $_NOT_
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2014-08-15 |
Clifford Wolf | Removed old doc references to $safe_pmux
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2014-08-15 |
Clifford Wolf | More idstring sort_by_* helpers and fixed tpl ordering...
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2014-08-15 |
Clifford Wolf | Added Frontend "+/" filename syntax for files from...
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2014-08-15 |
Clifford Wolf | document "techmap -map %<design-name>"
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2014-08-14 |
Clifford Wolf | Fixed bug in "read_verilog -ignore_redef"
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2014-08-14 |
Clifford Wolf | Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 |
Clifford Wolf | Changed the AST genWidthRTLIL subst interface to use...
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2014-08-14 |
Clifford Wolf | Added sig.{replace,remove,extract} variants for std...
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2014-08-14 |
Clifford Wolf | Fixed line numbers when using here-doc macros
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2014-08-14 |
Clifford Wolf | Fixed handling of task outputs
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2014-08-14 |
Clifford Wolf | Simplified $__arraymul techmap rule
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2014-08-14 |
Clifford Wolf | Added module->ports
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2014-08-14 |
Clifford Wolf | Refactoring of CellType class
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2014-08-14 |
Clifford Wolf | RIP $safe_pmux
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2014-08-14 |
Clifford Wolf | Some improvements in FSM mapping and recoding
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2014-08-14 |
Clifford Wolf | Added "abc -D" for setting delay target
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2014-08-14 |
Clifford Wolf | Updated ABC to 4935c2b946de
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2014-08-13 |
Clifford Wolf | Added techmap support for actual lookahead carry unit
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2014-08-13 |
Clifford Wolf | Preparations for lookahead ALU support in techmap.v
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2014-08-13 |
Clifford Wolf | Filter ANSI escape sequences from ABC output
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2014-08-13 |
Clifford Wolf | New interface for $__alu in techmap.v
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2014-08-13 |
Clifford Wolf | Added support for non-standard """ macro bodies
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2014-08-12 |
Clifford Wolf | Fixed handling of constant-true branches in proc_clean
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2014-08-12 |
Clifford Wolf | Added test_verific mode to tests/fsm/generate.py
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2014-08-12 |
Clifford Wolf | Fixed SigBit(RTLIL::Wire *wire) constructor
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2014-08-12 |
Clifford Wolf | Fixed building verific bindings
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2014-08-12 |
Clifford Wolf | Added multi-dim memory test (requires iverilog git...
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2014-08-11 |
Clifford Wolf | Another build fix by americanrouter (via reddit)
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2014-08-10 |
Clifford Wolf | Fixed FSM mapping for multiple reset-like signals
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2014-08-09 |
Clifford Wolf | Fixed "share" for complex scenarios with never-active...
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2014-08-09 |
Clifford Wolf | Do not share any $reduce_* cells (its complicated and...
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2014-08-09 |
Clifford Wolf | Some improvements in fsm_opt and fsm_map for FSM with...
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2014-08-08 |
Clifford Wolf | Improved FSM tests
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2014-08-08 |
Clifford Wolf | Another fsm_extract bugfix
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2014-08-08 |
Clifford Wolf | Fixed "fsm -export"
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2014-08-08 |
Clifford Wolf | Fixed sharing of reduce operator
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2014-08-08 |
Clifford Wolf | Fixed fsm_extract for wreduced muxes
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2014-08-08 |
Clifford Wolf | Added FSM test bench
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2014-08-08 |
Clifford Wolf | Added "sat -prove-skip"
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2014-08-07 |
Clifford Wolf | Fixed build with gcc-4.6
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2014-08-07 |
Clifford Wolf | Use "-keepdc" in "miter -equiv -flatten"
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2014-08-07 |
Clifford Wolf | Also allow "module foobar(input foo, output bar, ....
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2014-08-07 |
Clifford Wolf | Added adff2dff.v (for techmap -share_map)
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2014-08-06 |
Clifford Wolf | Added AST_MULTIRANGE (arrays with more than 1 dimension)
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2014-08-06 |
Clifford Wolf | Various improvements in memory_dff pass
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2014-08-05 |
Clifford Wolf | Various fixes and improvements in wreduce pass
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2014-08-05 |
Clifford Wolf | Removed old "constmap" from wreduce code
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2014-08-05 |
Clifford Wolf | Added support for truncating of wires to wreduce pass
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2014-08-05 |
Clifford Wolf | Cleanups and improvements in wreduce pass
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2014-08-05 |
Clifford Wolf | Added mux support to wreduce command
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2014-08-05 |
Clifford Wolf | Improved scope resolution of local regs in Verilog...
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2014-08-05 |
Clifford Wolf | Fixed AST handling of variables declared inside a functions...
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2014-08-04 |
Clifford Wolf | Added "show -signed"
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2014-08-04 |
Clifford Wolf | Added support for non-standard "module mod_name(.....
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2014-08-04 |
Clifford Wolf | Added RTLIL::IdString::in(...)
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2014-08-03 |
Clifford Wolf | Fixed "share" for memory read ports
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2014-08-03 |
Clifford Wolf | Added "wreduce" to some of the standard test benches
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2014-08-03 |
Clifford Wolf | Progress in "wreduce" pass
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2014-08-03 |
Clifford Wolf | Added "wreduce" command (work in progress)
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2014-08-03 |
Clifford Wolf | Added query() API to ModIndex
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2014-08-03 |
Clifford Wolf | Added ID() macro for static IdStrings
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2014-08-03 |
Clifford Wolf | Implemented recursive techmap
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2014-08-03 |
Clifford Wolf | Fixes in show command (related to new IdString)
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2014-08-02 |
Clifford Wolf | Implemented simplemap support for "techmap -extern"
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2014-08-02 |
Clifford Wolf | Fixed a va_list corruption in logv_error()
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2014-08-02 |
Clifford Wolf | Be more conservative with printing decimal numbers...
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2014-08-02 |
Clifford Wolf | Improved verilog output for ordinary $mux cells
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2014-08-02 |
Clifford Wolf | Bugfix in "techmap -extern"
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2014-08-02 |
Clifford Wolf | Removed at() method from RTLIL::IdString
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2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else
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2014-08-02 |
Clifford Wolf | More bugfixes related to new RTLIL::IdString
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2014-08-02 |
Clifford Wolf | Limit size of log_signal buffer to 100 elements
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2014-08-02 |
Clifford Wolf | Improvements in new RTLIL::IdString implementation
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2014-08-02 |
Clifford Wolf | Fixed a performance bug in opt_reduce
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2014-08-02 |
Clifford Wolf | Implemented new reference counting RTLIL::IdString
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2014-08-02 |
Clifford Wolf | Fixed memory corruption related to id2cstr()
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage
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2014-08-01 |
Clifford Wolf | Preparations for RTLIL::IdString redesign: cleanup...
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2014-08-01 |
Clifford Wolf | Added logfile hash to statistics footer
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2014-08-01 |
Clifford Wolf | Replaced sha1 implementation
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2014-08-01 |
Clifford Wolf | Added per-pass cpu usage statistics
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2014-08-01 |
Clifford Wolf | Added ModIndex helper class, some changes to RTLIL...
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2014-08-01 |
Clifford Wolf | Packed SigBit::data and SigBit::offset in a union
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2014-08-01 |
Clifford Wolf | Consolidated hana test benches into fewer files
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2014-08-01 |
Clifford Wolf | Added "test_autotb -n <num_iter>" option
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2014-07-31 |
Clifford Wolf | Renamed modwalker.h to modtools.h
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2014-07-31 |
Clifford Wolf | Various cleanups in Makefile, Renamed default configurations
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2014-07-31 |
Clifford Wolf | Added compiler + compiler version + compiler flags...
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2014-07-31 |
Clifford Wolf | Fixed build of verific bindings
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added...
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2014-07-31 |
Clifford Wolf | Added "trace" command
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2014-07-31 |
Clifford Wolf | Added RTLIL::Monitor
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2014-07-31 |
Clifford Wolf | Added module->design and cell->module, wire->module...
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-31 |
Clifford Wolf | Renamed "stdcells.v" to "techmap.v"
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2014-07-31 |
Clifford Wolf | Added "techmap -assert"
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