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Techmap flops before ABC again
2019-06-01
Eddie Hung
Techmap flops before ABC again
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2019-06-01
Eddie Hung
parse_xaiger to cope with flops
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2019-05-31
Eddie Hung
ABC9 to understand flops
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2019-05-31
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-05-31
Eddie Hung
Throw out unused code inherited from abc
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2019-05-30
Eddie Hung
Fix issue where keep signal became PI, but also box...
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2019-05-30
Eddie Hung
read_xaiger() to name box signals
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2019-05-30
Eddie Hung
Fix spelling
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2019-05-30
Eddie Hung
Remove whitebox attribute from DRAMs for now
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2019-05-30
Eddie Hung
Do not re-sort box_module ports
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2019-05-30
Eddie Hung
Remove whitespace
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2019-05-30
Eddie Hung
Revert "Re-enable &dc2"
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2019-05-30
Eddie Hung
Do not double count LUT1s
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2019-05-30
Eddie Hung
Carry in/out to be the last input/output for chains...
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2019-05-30
Eddie Hung
Re-enable &dc2
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2019-05-30
Eddie Hung
Reduce -W to 160
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2019-05-30
Eddie Hung
Some more realistic delays...
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2019-05-30
Eddie Hung
Erase all boxes before stitching
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2019-05-29
Eddie Hung
Call &if with -W 250
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2019-05-29
Eddie Hung
Bump ABC
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2019-05-29
Eddie Hung
Rename to #23
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2019-05-29
Eddie Hung
Add abc_test024
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2019-05-29
Eddie Hung
Fix abc_test024
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2019-05-29
Eddie Hung
Add some debug to abc9
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2019-05-28
Eddie Hung
Add abc9_test022
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2019-05-28
Eddie Hung
Fix for abc9_test022
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2019-05-28
Eddie Hung
Small improvement
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2019-05-28
Eddie Hung
From master
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2019-05-28
Eddie Hung
From master
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2019-05-28
Eddie Hung
Typo
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2019-05-28
Eddie Hung
Update from master
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2019-05-28
Eddie Hung
Update README.md from master
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2019-05-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-28
Eddie Hung
read_aiger to only clean own design
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2019-05-28
Eddie Hung
Misspell
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2019-05-28
Eddie Hung
If driver not found, use LUT2
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2019-05-28
Eddie Hung
Parse "a" extension and boxes from map file
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2019-05-28
Eddie Hung
Map file to include boxes not CI/CO
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2019-05-28
Eddie Hung
Make MUXF{7,8} and CARRY4 whitebox
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2019-05-28
Eddie Hung
Re-enable lib_whitebox
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2019-05-28
Eddie Hung
Disconnect all ABC boxes too
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2019-05-27
Eddie Hung
Remove unused function
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2019-05-27
Eddie Hung
parse_xaiger to not parse symbol table
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2019-05-27
Eddie Hung
Parse without wideports
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2019-05-27
Eddie Hung
Remove mapped_mod when done
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2019-05-27
Eddie Hung
Instantiate cell type (from sym file) otherwise 'clean...
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2019-05-27
Eddie Hung
Add 'cinput' and 'coutput' to symbols file for boxes
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2019-05-26
Eddie Hung
Fix "a" connectivity
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2019-05-26
Eddie Hung
Blackboxes
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2019-05-26
Eddie Hung
ABC9 to call &sweep
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2019-05-26
Eddie Hung
Fix padding, remove CIs from undriven_bits before erasing...
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2019-05-26
Eddie Hung
Typo
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2019-05-26
Eddie Hung
Muck about with LUT delays some more
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2019-05-26
Eddie Hung
Combine ABC_COMMAND_LUT
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2019-05-26
Eddie Hung
Fix "a" extension
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2019-05-26
Eddie Hung
Fix "write_xaiger", and to write each box contents...
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2019-05-26
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-25
Eddie Hung
Revert enable check
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2019-05-25
Eddie Hung
Try new LUT delays
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2019-05-25
Eddie Hung
Fix init
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2019-05-25
Eddie Hung
Fix typos
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2019-05-25
Eddie Hung
Add more tests
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2019-05-25
Eddie Hung
Call proc
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2019-05-25
Eddie Hung
opt_rmdff to optimise even in presence of enable signal...
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2019-05-25
Eddie Hung
Fix duplicate driver
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2019-05-24
Eddie Hung
Add comments
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2019-05-24
Eddie Hung
Resolve @cliffordwolf review, set even if !has_init
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2019-05-24
Eddie Hung
Add &fraig and &mfs back
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2019-05-24
Eddie Hung
Transpose CARRY4 delays
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/opt_rmdff...
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2019-05-23
Eddie Hung
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
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2019-05-23
Eddie Hung
Fix spacing
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2019-05-23
Eddie Hung
Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23
Eddie Hung
Add opt_rmdff tests
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2019-05-23
Eddie Hung
opt_rmdff to work on $dffe and $_DFFE_*
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2019-05-23
Eddie Hung
Add whitebox support to DRAM
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2019-05-22
Eddie Hung
shift register inference before mux
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2019-05-22
Eddie Hung
Fix/workaround symptom unveiled by #1023
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2019-05-22
Eddie Hung
Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces
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2019-05-22
Eddie Hung
Rename label
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2019-05-22
Eddie Hung
Try again
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2019-05-21
Eddie Hung
Fix warning
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2019-05-21
Eddie Hung
Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21
Eddie Hung
Pad all boxes so that all input/output connections...
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2019-05-21
Eddie Hung
Modify LUT area cost to be same as old abc
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-03
Eddie Hung
More testing
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2019-05-03
Eddie Hung
Fix spacing
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2019-05-03
Eddie Hung
Add quick-and-dirty specify tests
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into clifford...
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2019-05-03
Eddie Hung
Rename cells_map.v to prevent clash with ff_map.v
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2019-05-03
Eddie Hung
iverilog with simcells.v as well
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2019-05-03
Eddie Hung
log_warning_noprefix -> log_warning as per review
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2019-05-03
Eddie Hung
For hier_tree::Elaborate() also include SV root modules...
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2019-05-03
Eddie Hung
Fix verific_parameters construction, use attribute...
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2019-05-03
Eddie Hung
WIP -chparam support for hierarchy when verific
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2019-05-03
Eddie Hung
verific_import() changes to avoid ElaborateAll()
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2019-05-03
Eddie Hung
Revert "synth_xilinx to call dffinit with -noreinit"
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2019-05-03
Eddie Hung
If init is 1'bx, do not add to dict as per @cliffordwolf
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