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dev-arm: Avoid code duplication in Pl111
2020-07-30 Giacomo Travaglinidev-arm: Avoid code duplication in Pl111
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Relax size constraint on AMBA ID registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Fix DTB autogen for HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make the Sp805 use the new ArmInterruptPin...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Sp804 use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Make Pl011 UART use the ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-30 Giacomo Travaglinidev-arm: Introduce the active boolean for ArmInterruptPin
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive PPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Implement LevelSensitive SPIs in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-23 Giacomo Travaglinidev-arm: Gicv3 maintenance interrupt never cleared
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Check for security attribute when writing...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-21 Giacomo Travaglinidev-arm: Remove SPI/PPI range check in Gicv3 class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-15 Giacomo Travagliniarch-arm: AddressSize check on translateMmuOff for...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Fix coding style in self_debug.[cc, hh]
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Remove getters/setters from SelfDebug class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Fix pmc == on SelfDebug
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-13 Giacomo Travagliniarch-arm: Move breakpoint/watchpoint check out of the TLB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Style fixes for src/dev/arm/gic_v2.hh
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Implement Level Sensitive PPIs in GICv2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Use getIntConfig when reading/writing GICD_ICFGR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-11 Giacomo Travaglinidev-arm: Move GICv2 intConfig for consistency
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-07-07 Michiel W. van Tolcpu-o3: Avoid passing ReExec 'faults' on CPU tracing...
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2020-06-26 Giacomo Travagliniext: Remove dead code from results.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-26 Giacomo Travagliniext: Remove dead code from main.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-26 Giacomo Travagliniext: Remove dead code from configuration.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-25 Giacomo Travaglinisim: Fix -Werror=maybe-uninitialized in system.cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-25 Giacomo Travagliniarch-arm: Fix arm switcheroo regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-22 Michiel W. van Tolcpu: Use new InstRecord faulting flag in cpu models
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2020-06-22 Michiel W. van Tolsim: Add faulting flag to instruction tracing interface
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2020-06-22 Giacomo Travagliniscons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-19 Michiel W. van Tolarch-arm: Add missing isFirstMicroop flags on uop sequences
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2020-06-18 Giacomo Travagliniext: Remove dead code from runner.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from handlers.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from fixture.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from loader.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from helper.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove dead code from test_util.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove LogWrapper/TestLogWrapper from log.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Fix the MakeFixture setup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Avoid specifying empty interfaces and embrace...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travagliniext: Remove sandbox module from testlib
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-18 Giacomo Travaglinitests: log_call is not returning any value
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-14 Giacomo Travaglinitests: Use default None argument in makeArmSystem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-06-08 Giacomo Travaglinimisc: Remove any reference to the ALPHA ISA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-20 Michiel W. van Tolpython: Make DOT config generation optional
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2020-05-14 Giacomo Travaglinimisc: Add Arm contributions to gem5-20 RELEASE-NOTES.md
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-12 Jason Lowe-Powerscons: Update python-config flags for python3.8
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2020-05-12 Giacomo Travagliniscons: Add readCommandWithReturn helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-11 Timothy Hayesmem-ruby: MESI_Two_Level missing function compilation fix
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2020-05-11 Timothy Hayesmem-ruby: MOESI_CMP_directory sync fix
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2020-05-09 Giacomo Travagliniarch-arm: SVE instruction in EL1s cannot be trapped...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: CPTR.FPEN controlling SVE enablement
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: Remove checkSveTrap method
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travaglinipython: Manually convert float to int when using %x
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Make cpt_upgraders python3 compatible
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Port git hooks to python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-04 Giacomo Travagliniarch-arm: Decode SEVL instruction for A32 and T32 IS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travagliniconfigs: Do not require args.kernel to be set in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travaglinisim, arch-arm: Restore capability of running without...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: SVE instructions do not use AHP format
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: Do not increment exponent if FPSCR.FZ in...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Use workloads.py in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Produce list of workload types in workloads.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Add an example workloads module
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --machine-type option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --semi-path option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-19 Giacomo Travagliniarch-sparc: MAP_32BIT does not exist on solaris
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travaglinitests: Run realview(64) tests with VExpress_GEM5_Foundation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch-arm: Override ISA::takeOverFrom for the Arm ISA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch, cpu: Add a takeOverFrom method for switching...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch-arm: Remove unnecessary haveGICv3CPUInterface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinitests: Fail checkpoint regressions if no cpt has been...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinitests: Reduce checkpoint interval used by realview...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinidev-arm: Fix checkpointing for the GenericTimer
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travagliniarch-arm: Handle empty object_file scenario in ArmFsWorkload
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-09 Adrian Herreradev-arm: Add VExpress_GEM5_Foundation platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-08 Adrian Herreraarch-arm, dev-arm: Autogen PSCI node in DTB
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-06 Giacomo Travagliniarch-arm: CNTHCTL trap to EL2 only if ARMv8.6-ECV implemented
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-01 Giacomo Travagliniconfigs: Enabling SimObj CLI for baremetal platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-31 Adrian Herreraarch-arm, dev-arm: WakeRequest implementation
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2020-03-30 Adrian Herreradev-arm: Adjust idreg value in RealViewCtrl
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-30 Giacomo Travaglinidev-arm: Fix pci_mem_base setting in VExpress_GEM5_Base
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-26 Giacomo Travaglinidev-arm: Don't use args and kwargs on attachIO
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Use ArmFsWorkload for Arm baremetal
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Adrian Herreracpu: IntrControl, clear all and check helpers
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Initialize atags_addr in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Enable Semihosting for baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Make --disk-image optional in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-24 Giacomo Travagliniarch-arm: Make load_addr_mask=0 for ArmFsLinux only
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-24 Giacomo Travagliniarch-arm: Fix aapcs32/aapcs64 compilation issues
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-23 Giacomo Travaglinidev-arm: Add flash1 memory to VExpress_GEM5 platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-23 Adrian Herreradev-arm: Instantiate FVPBasePwrCtrl in VExpress_GEM5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-20 Timothy Hayesmem-ruby: MESI_Three_Level discriminate L0 invalidation...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-20 Timothy Hayesmem-ruby: MESI_Three_Level fix L1 MRU absence
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-20 Timothy Hayesmem-ruby: MESI_Three_Level fix L1 in_port ranks
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-20 Timothy Hayesmem-ruby: MESI_Three_level HTML reference generation fix
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2020-03-19 Giacomo Travaglinitests: Add --bin-path option to insttest regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-19 Giacomo Travagliniarch-arm: Fix ArmSystem::_resetAddr evalutation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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