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Update todo for more features to verificsva.cc
2018-03-16 Clifford WolfUpdate todo for more features to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-16 Clifford WolfUpdate todo for more features to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-16 Clifford WolfAdd todo for more features to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-15 Clifford WolfImprove import of memories via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-14 Clifford WolfFix handling of SV compilation units in Verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-12 Clifford WolfAdd "expose -input"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-12 Clifford WolfAdd "setundef -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-10 Clifford WolfFix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-10 Clifford WolfFix variable name typo in verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-10 Clifford WolfAdd support for trivial SVA sequences and properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-10 Clifford WolfFix handling of src attributes in flatten
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-08 Clifford WolfRemove debug prints from yosys-smtbmc VCD writer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-08 Clifford WolfUse Verific hier_tree component for elaboration
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-07 Clifford WolfCheck results of (check-sat) in yosys-smtbmc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-07 Clifford WolfFix Verific handling of "assert property (..);" in...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-07 Clifford WolfAdd "verific -import -V"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-07 Clifford WolfSet Verific db_preserve_user_nets flag
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-07 Clifford WolfAdd Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-06 Clifford WolfAdd "memory_nordff" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfUpdate comment about supported SVA in verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfAdd SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfAdd SVA first_match() support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfAdd SVA within support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfAdd support for SVA sequence intersect
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfAdd get_fsm_accept_reject for parsing SVA properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-06 Clifford WolfSimplified SVA "until" handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-05 Clifford WolfImporove yosys-smtbmc error handling, Improve VCD output
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfFix connwrappers help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfImprove handling of warning messages
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfUpdate copyright header
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfImprove SMT2 encoding of $reduce_{and,or,bool}
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfFix a hangup in yosys-smtbmc error handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfAdd proper SVA seq.triggered support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfAdd "synth -noshare"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfAdd Verific SVA support for "seq and seq" expressions
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfRefactor Verific SVA importer property parser
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-04 Clifford WolfAdd VerificClocking class and refactor Verific DFF...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-03 Clifford WolfImproved error handling in yosys-smtbmc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-03 Clifford WolfAdd SVA support for sequence OR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-03 Clifford WolfTerminate running SMT solver when smtbmc is terminated
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-03 Clifford WolfFix smtbmc smtc/aiw parser for wire names containing []
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-02 Clifford WolfFix handling of SVA "until seq.triggered" properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-02 Clifford WolfUpdate SVA cheat sheet in verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-01 Clifford WolfFix in Verific SVA importer handling of until_with
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-01 Clifford WolfMangle names with square brackets in VCD files to work...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-01 Clifford WolfFixes and improvements in Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-03-01 Clifford WolfAdd $rose/$fell support to Verific bindings
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-28 Clifford WolfMerge branch 'verificsva-ng'
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2018-02-28 Clifford WolfAdd support for PRIM_SVA_UNTIL to new SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-28 Clifford WolfAdd DFSM generator to verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-28 Clifford WolfContinue refactoring of Verific SVA importer code
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-27 Clifford WolfMajor redesign of Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-27 Clifford WolfAdd -lz for verific builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfAdd handling of verific OPER_REDUCE_NOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfAdd handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfAdd handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfAdd "SVA syntax cheat sheet" comment to verificsva.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfAdd $dlatchsr support to clk2fflogic
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2018-02-26 Clifford WolfSmall fixes and improvements in $allconst/$allseq handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-26 Clifford WolfFix opt_rmdff handling of $dlatchsr
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-23 Clifford WolfMerge branch 'forall'
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2018-02-23 Clifford WolfAdd smtbmc support for exist-forall problems
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-22 Clifford WolfAdd Verific SVA support for ranges in repetition operator
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2018-02-21 Clifford WolfAdd support for SVA throughout via Verific
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2018-02-20 Clifford WolfAdd support for mockup clock signals in yosys-smtbmc...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-19 Clifford WolfMerge pull request #507 from cr1901/msys2
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2018-02-18 Clifford WolfAdd support for SVA sequence concatenation ranges via...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-18 Clifford WolfAdd support for SVA until statements via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-18 Clifford WolfMove Verific SVA importer to extra C++ source file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-18 Clifford WolfMerge Verific SVA preprocessor and SVA importer
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2018-02-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
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2018-02-15 Clifford WolfImprove handling of "bus" pins in liberty front-end...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-15 Clifford WolfFix verific PRIM_SVA_AT handling in properties with...
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2018-02-13 Clifford WolfFixed yosys-config for binary distributions with Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-13 Clifford WolfRecognize stand-alone obj pattern even when it contains...
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2018-02-08 Clifford WolfFix handling of zero-length cell connections in SMT2...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
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2018-02-03 Clifford WolfDo not create deep backtraces unless in ENABLE_DEBUG...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-02-03 Clifford WolfMerge pull request #488 from azonenberg/for_clifford
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2018-02-03 Clifford WolfFixed gcc 7.2 "statement will never be executed" warning
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2018-02-01 Clifford WolfFix single-bit $stable handling in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-31 Clifford WolfAdd Verific attribute handling for assert/assume/cover...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-29 Clifford WolfFix smtio.py for large SMT2 S-expressions
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2018-01-28 Clifford WolfFix permissions on verific vdb files
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2018-01-23 Clifford WolfFixed handling of synchronous and asynchronous assertion...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-19 Clifford WolfUse "strip -S" instead of "strip -d" for Mac OS X compatibility
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-19 Clifford WolfImprove log messages in equiv_make
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-18 Clifford WolfMove user-provided smt2 info stmts to the top of the...
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2018-01-17 Clifford WolfStrip debug symbols from binaries on install
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2018-01-09 Clifford WolfAdd "dffinit -highlow" and fix synth_intel
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-07 Clifford WolfAdd support for "yosys -E"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-07 Clifford WolfBugfix in hierarchy blackbox module port width handling
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2018-01-07 Clifford WolfUpdate ABC to hg rev 6e3c24b3308a
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-05 Clifford WolfMerge pull request #479 from Fatsie/latch_without_data
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2018-01-05 Clifford WolfBugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-01-04 Clifford WolfMerge pull request #480 from Fatsie/liberty_value_expression
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2018-01-04 Clifford WolfTemporarily derive blackbox modules in hierarchy to...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2017-12-24 Clifford WolfAdd "no driver for signal bit" error msg to btor back-end
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2017-12-24 Clifford WolfBugfix in verilog_defaults argument parser
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