| 2019-10-02 |
Marc Mari Barcelo | dev-arm: Fix address used to update the SMMUv3 Walk...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-10-02 |
Giacomo Travaglini | arch-arm: Create helper for sending events (SEV)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | dev-arm: Conditionally enable HDLcd when doing DTB...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | dev-arm: Add HDLcd DTB autogeneration
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-19 |
Giacomo Travaglini | arch-arm: PSTATE.PAN changes should inval cached regs...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-18 |
Adrian Herrera | system-arm: Add ITS node in platforms/vexpress_gem5_v2_base...
|
commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: Fix Data Abort ISS when caused by Atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: ISV bit in DataAbort should check for translation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-18 |
Giacomo Travaglini | arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-16 |
Giacomo Travaglini | dev-arm: Allow IOMMU binding to HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-13 |
Giacomo Travaglini | dev-arm: Store the IOMMU reference from within the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-13 |
Giacomo Travaglini | dev: Enable DTB IOMMU binding with a DMA object
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Reset HPPI when clearing an LPI
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Add resetHppi method in the GICv3 cpu interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Cleanup GICv3 initialization
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Initialize GICD_TYPER once at construction...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Writes to IGRPEN1_EL3 triggering update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Fix GICv3 ITS cmdq wrapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-09 |
Giacomo Travaglini | dev-arm: Implement message-based SPIs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-07 |
Giacomo Travaglini | dev-arm: Add GICD_SGIR register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev: Enable Terminal output's dump to stdout
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: State update when setting MISCREG_ICC_IGRPENx...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Add read/writeBanked helpers to GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: Add explicit AArch64 MiscReg banking
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: Use same template across all MSR inst
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Add GICv3 unimplemented Hyp Active Priorities...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Allow 32-bit access to GITS_TYPER
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Cpu interface groupEnabled check for global...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Check if INTID group is enabled when reading...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Writing GICD_CTLR should trigger an update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Rewrite GICv3 update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Fix GICv3 IGRPMOD writes
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: SGI registers undecoded in AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Giacomo Travaglini | dev-arm: Fix SGI generation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-09-06 |
Adrian Herrera | dev-arm: Gicv3 ITS device tree autogen
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-06 |
Adrian Herrera | dev-arm: modify GICv3 ITS default addr
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-05 |
Giacomo Travaglini | dev-arm: Improper translation slot release in SMMUv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-05 |
Jan-Peter Larsson | dev-arm: Implement invalidateASID in SMMUv3 WalkCache
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-09-05 |
Adrian Herrera | dev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-30 |
Giacomo Travaglini | arm,kvm: Fix python imports from global namespace
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-26 |
Giacomo Travaglini | dev-arm: Fix GICv3 ITS indexing error
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-26 |
Giacomo Travaglini | dev-arm: Fix GITS_BASER initialization/access
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-22 |
Giacomo Travaglini | dev-arm: Start using GITS_CTLR.quiescent bit
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-22 |
Giacomo Travaglini | dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-22 |
Adrian Herrera | dev-arm,system-arm: missing GICv3 ranges property
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | dev-arm: Add redistributor-stride property to GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | arch-arm: Replace occ of opModeToEL(currOpMode/cpsr...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | arch-arm: Replace direct use cpsr.el with currEL helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | arch-arm: Overload currEL helper with CPSR argument
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | arch-arm: Rewrite the currEL helper method to use opModeToEL
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | dev-arm: Add GITS_PIDR2 register to the ITS memory map
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-20 |
Giacomo Travaglini | dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRx
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-12 |
Giacomo Travaglini | dev-arm: Enable DTB autogeneration in GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-12 |
Giacomo Travaglini | dev-arm: Fix PCI node's interrupt-map property
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-12 |
Giacomo Travaglini | dev-arm: Use FdtState to generate GIC properites
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-12 |
Giacomo Travaglini | python: FdtState using interrupt-cells
|
commit | commitdiff | tree |
| 2019-08-07 |
Giacomo Travaglini | dev-arm: Perform SMMUv3 CFG Invalidation at device...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-08-05 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1-PAN, Privileged access...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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commit | commitdiff | tree |
| 2019-08-05 |
Giacomo Travaglini | arch-arm: Rewrite MSR immediate instruction class
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-30 |
Giacomo Travaglini | dev-arm: Rewrite SMMUv3 Commands
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: Fix SMMUv3 CMDQ wrapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: Polish SMMUv3 CMDQ setup
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: Define enum masks for SMMU_CR0 register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: TnSZ fields need to be cached in SMMUv3::ConfigCache
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: SMMUv3 Table walks using TnSZ
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Giacomo Travaglini | dev-arm: Use override keyword for SMMUv3 PTOPS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-25 |
Michiel Van Tol | dev-arm: Add 16K granule support to SMMUv3 model
|
commit | commitdiff | tree |
| 2019-07-19 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1-HPD, Hierarchical permission...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-19 |
Giacomo Travaglini | arch-arm: Add HPD bit for TCR_EL2/EL3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-19 |
Giacomo Travaglini | arch-arm: Clean Fault generation when processing Long...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-19 |
Matteo Andreozzi | dev-arm: clang compatibility fix, added missing overrides
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-18 |
Gabor Dozsa | arch-arm: Add first-/non-faulting load instructions
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-18 |
Gabor Dozsa | sim: Add getter to fault virtual address
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-17 |
Giacomo Travaglini | arch-arm: Use ExceptionLevel type in TlbEntry
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-16 |
Giacomo Travaglini | dev-arm: Fix SMMUv3 ContextDescriptor pointer shift
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-07-16 |
Giacomo Travaglini | cpu: isDrained renamed to isCpuDrained
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-28 |
Michiel W. van Tol | base: Add argument to Coroutine class to not run on...
|
commit | commitdiff | tree |
| 2019-06-26 |
Anouk Van Laer | arch, arm: Update miscRegs in getTE
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-26 |
Giacomo Travaglini | dev-arm: Remove un-needed Q_CONS_PROD_MASK macro
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-26 |
Adrian Herrera | dev-arm: drain implementation for SMMUv3
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-26 |
Adrian Herrera | dev-arm: pending SMMU transl update on constructor...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-20 |
Giacomo Travaglini | configs: Fix NULL dram-lowp regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-17 |
Giacomo Travaglini | arch-arm: Move the memacc_code before op_wb in fp loads
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-17 |
Giacomo Travaglini | dev-arm: Reapply GICv3 changes that were lost during...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-09 |
Giacomo Travaglini | base: Provide a getter for Fiber::started boolean variable
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-09 |
Giacomo Travaglini | base: Rename TestFiber into SwitchingFiber
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-07 |
Giacomo Travaglini | arch-arm: Fix WalkerState,Descriptors default constructor
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-06-06 |
Stanislaw Czerniawski | dev-arm: Implement a SMMUv3 model
- Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-05-24 |
Giacomo Travaglini | arch-arm: Fix fallthrough when trapping at EL2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-05-23 |
Giacomo Travaglini | arch-arm: Trap virtual accesses to GICv3 SGI registers
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-05-23 |
Giacomo Travaglini | arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
commit | commitdiff | tree |
| 2019-05-23 |
Giacomo Travaglini | arch-arm: Change mcrMrc15TrapToHyp signature
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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