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Remove topo sort no-loop assertion, with test
2019-04-16
Eddie Hung
Re-enable partsel.v test
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tree
2019-04-16
Eddie Hung
abc9 to call "setundef -zero" behaving as for abc
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2019-04-16
Eddie Hung
NULL check before use
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tree
2019-04-16
Eddie Hung
WIP for box support
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tree
2019-04-16
Eddie Hung
ABC to read_box before reading netlist
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tree
2019-04-16
Eddie Hung
Make cells.box whiteboxes not blackboxes
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2019-04-16
Eddie Hung
read_verilog cells_box.v before techmap
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2019-04-16
Eddie Hung
synth_xilinx: before abc read +/xilinx/cells_box.v
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tree
2019-04-16
Eddie Hung
Add +/xilinx/cells_box.v containing models for ABC...
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2019-04-16
Eddie Hung
For 'stat' do not count modules with abc_box_id
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tree
2019-04-16
Eddie Hung
Do not call abc on modules with abc_box_id attr
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2019-04-16
Eddie Hung
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
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2019-04-16
Eddie Hung
Revert #895
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2019-04-16
Eddie Hung
Use abc_box_id
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2019-04-16
Eddie Hung
Check abc_box_id attr
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tree
2019-04-16
Eddie Hung
Add abc_box_id attribute to MUXF7/F8 cells
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2019-04-16
Eddie Hung
Merge branch 'xaig' into xc7mux
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tree
2019-04-16
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-13
Eddie Hung
Forgot backslashes
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2019-04-13
Eddie Hung
Handle __dummy_o__ and __const[01]__ in read_aiger...
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2019-04-13
Eddie Hung
abc to ignore __dummy_o__ and __const[01]__ when re...
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2019-04-13
Eddie Hung
Output __const0__ and __const1__ CIs
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2019-04-13
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-13
Eddie Hung
Fix inout handling for -map option
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2019-04-12
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
Use -map instead of -symbols for aiger
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2019-04-12
Eddie Hung
ci_bits and co_bits now a list, order is important...
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2019-04-12
Eddie Hung
Also cope with duplicated CIs
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2019-04-12
Eddie Hung
WIP
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tree
2019-04-12
Eddie Hung
Comment out
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tree
2019-04-12
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-12
Eddie Hung
Cope with an output having same name as an input (i...
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-04-12
Eddie Hung
PI before CI
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2019-04-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-04-11
Eddie Hung
Fix ordering of when to insert zero index
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
More unused
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2019-04-11
Eddie Hung
Merge remote-tracking branch 'origin/pmux2shiftx' into...
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2019-04-11
Eddie Hung
Remove unused
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2019-04-11
Eddie Hung
Fixes
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2019-04-11
Eddie Hung
WIP
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2019-04-11
Eddie Hung
Spelling fixes
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2019-04-11
Eddie Hung
Add default entry to testcase
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2019-04-11
Eddie Hung
Recognise default entry in case even if all cases covered...
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2019-04-11
Eddie Hung
Fix cells_map.v some more
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2019-04-11
Eddie Hung
More fine tuning
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2019-04-11
Eddie Hung
Fix cells_map.v
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2019-04-11
Eddie Hung
Fix typo
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2019-04-11
Eddie Hung
Juggle opt calls in synth_xilinx
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2019-04-11
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-11
Eddie Hung
Add non-input bits driven by unrecognised cells as...
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2019-04-11
Eddie Hung
WIP for cells_map.v -- maybe working?
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2019-04-10
Eddie Hung
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
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2019-04-10
Eddie Hung
Fix for when B_SIGNED = 1
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2019-04-10
Eddie Hung
Update doc for synth_xilinx
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2019-04-10
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-04-10
Eddie Hung
parse_aiger() to rename all $lut cells after "clean"
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2019-04-10
Eddie Hung
ff_map.v after abc
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2019-04-10
Eddie Hung
Tidy up
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2019-04-10
Eddie Hung
Move map_cells to before map_luts
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2019-04-10
Eddie Hung
WIP for $shiftx to wide mux
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2019-04-10
Eddie Hung
Update LUT delays
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2019-04-10
Eddie Hung
synth_* with -retime option now calls abc with -D 1...
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2019-04-10
Eddie Hung
Revert "abc -dff now implies "-D 0" otherwise retiming...
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2019-04-10
Eddie Hung
Revert ""&nf -D 0" fails => use "-D 1" instead"
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2019-04-10
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-04-09
Eddie Hung
Add cells.lut to techlibs/xilinx/
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2019-04-09
Eddie Hung
synth_xilinx to call abc with -lut +/xilinx/cells.lut
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2019-04-09
Eddie Hung
Add delays to cells.box
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2019-04-09
Eddie Hung
Add "-lut <file>" support to abc9
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2019-04-09
Eddie Hung
synth_xilinx with abc9 to use -box
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2019-04-09
Eddie Hung
Add techlibs/xilinx/cells.box
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2019-04-09
Eddie Hung
Add "-box" option to abc9
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2019-04-09
Eddie Hung
Add 'setundef -zero' call prior to aigmap in abc9
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2019-04-09
Eddie Hung
Comment out
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2019-04-09
Eddie Hung
Add support for synth_xilinx -abc9 and ignore abc9...
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2019-04-08
Eddie Hung
More space fixing
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2019-04-08
Eddie Hung
Fix spacing
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-08
Eddie Hung
$_XILINX_SHREG_ to preserve src attribute
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2019-04-08
Eddie Hung
Update CHANGELOG
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2019-04-08
Eddie Hung
Merge branch 'undo_pr895' into xc7srl
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2019-04-08
Eddie Hung
Undo #895 by instead setting an attribute
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2019-04-08
Eddie Hung
Cope with undoing #895
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2019-04-08
Eddie Hung
Revert "Remove handling for $pmux, since #895"
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2019-04-06
Eddie Hung
Call shregmap twice -- once for variable, another for...
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Add retime test
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2019-04-05
Eddie Hung
Fix S0 -> S1
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2019-04-05
Eddie Hung
Move dffinit til after abc
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2019-04-05
Eddie Hung
Merge branch 'eddie/fix_retime' into xc7srl
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2019-04-05
Eddie Hung
Move techamp t:$_DFF_?N? to before abc call
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2019-04-05
Eddie Hung
Retry
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2019-04-05
Eddie Hung
"&nf -D 0" fails => use "-D 1" instead
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2019-04-05
Eddie Hung
Resolve @daveshah1 comment, update synth_xilinx help
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2019-04-05
Eddie Hung
synth_xilinx to techmap FFs after abc call, otherwise...
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2019-04-05
Eddie Hung
abc -dff now implies "-D 0" otherwise retiming doesn...
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2019-04-05
Eddie Hung
techmap inside map_cells stage
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