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2019-01-30	Giacomo Gabrielli	arch,cpu: Add vector predicate registers Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>	commit \| commitdiff \| tree
2018-12-03	Giacomo Gabrielli	base: Add type alias for raw pointer in RefCountingPtr Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>	commit \| commitdiff \| tree
2018-08-10	Giacomo Gabrielli	arm: Add support for RCpc load-acquire instructions...	commit \| commitdiff \| tree
2015-05-26	Giacomo Gabrielli	arm: Implement some missing syscalls (SE mode)	commit \| commitdiff \| tree
2015-05-05	Giacomo Gabrielli	arm: enable DCZVA by default in SE mode	commit \| commitdiff \| tree
2015-03-02	Giacomo Gabrielli	arm: Remove unnecessary dependencies between AArch64...	commit \| commitdiff \| tree
2014-01-24	Giacomo Gabrielli	cpu: Add support for Memory+Barrier instruction types...	commit \| commitdiff \| tree
2014-01-24	Giacomo Gabrielli	mem: Add flag to request if it was generated by a...	commit \| commitdiff \| tree
2014-01-24	Giacomo Gabrielli	mem: Add support for a security bit in the memory system	commit \| commitdiff \| tree
2012-03-01	Giacomo Gabrielli	ARM: fix bits-to-fp conversion function declarations.	commit \| commitdiff \| tree
2011-08-19	Giacomo Gabrielli	O3: Squash the violator and younger instructions instead...	commit \| commitdiff \| tree
2011-07-15	Giacomo Gabrielli	O3: Create a pipeline activity viewer for the O3 CPU...	commit \| commitdiff \| tree
2011-02-23	Giacomo Gabrielli	ARM: NEON instruction templates modified to set the...	commit \| commitdiff \| tree
2011-02-12	Giacomo Gabrielli	O3: Fix pipeline restart when a table walk completes...	commit \| commitdiff \| tree
2011-02-12	Giacomo Gabrielli	O3: Fix a few bugs in the TableWalker object.	commit \| commitdiff \| tree
2011-02-12	Giacomo Gabrielli	O3: Enhance data address translation by supporting...	commit \| commitdiff \| tree
2010-12-08	Giacomo Gabrielli	O3: Make all instructions that write a misc. register...	commit \| commitdiff \| tree
2010-11-15	Giacomo Gabrielli	CPU/ARM: Add SIMD op classes to CPU models and ARM...	commit \| commitdiff \| tree

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