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Merge remote-tracking branch 'upstream/master'
2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-10-08
Clifford Wolf
Improve Verific importer blackbox handling
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2018-10-08
Clifford Wolf
Add "write_edif -attrprop"
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2018-10-08
Clifford Wolf
Fix compiler warning in verific.cc
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2018-10-08
Tim Ansell
Fix misspelling in issue_template.md
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2018-10-08
Adrian Wheeldon
Fix IdString M in setup_stdcells()
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2018-10-08
Clifford Wolf
Add inout ports to cells_xtra.v
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2018-10-08
Tim Ansell
xilinx: Adding missing inout IO port to IOBUF
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2018-10-08
Tom Verbeure
Fix for issue 594.
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2018-10-08
Dan Gisselquist
Add read_verilog $changed support
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2018-10-08
David Shah
ecp5: Don't map ROMs to DRAM
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2018-10-08
Clifford Wolf
Fix handling of $past 2nd argument in read_verilog
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2018-10-08
Clifford Wolf
Update to v2 YosysVS template
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2018-10-08
Clifford Wolf
Add "read_verilog -noassert -noassume -assert-assumes"
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2018-10-08
Clifford Wolf
Added support for ommited "parameter" in Verilog-2001...
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2018-10-08
Clifford Wolf
Update CHANGELOG
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2018-10-08
Miodrag Milanovic
added prefix to FDirection constants, fixing windows...
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2018-10-08
Clifford Wolf
Update CHANGLELOG
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2018-10-08
Clifford Wolf
Update Changelog
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2018-10-08
Miodrag Milanovic
Fix Cygwin build and document needed packages
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2018-10-08
acw1251
Fixed typo in "verilog_write" help message
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2018-09-17
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-08-27
Jim Lawson
Merge branch 'master' into firrtl+modules+shiftfixes
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2018-08-27
Jim Lawson
Remove unused functions.
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2018-08-23
Jim Lawson
Add support for module instances.
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