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cpu: Add byteEnable assertions to readMem and initateMemRead
2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMemRead
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Adrian Herreradev-arm: GenericTimer, configurable base and low freqs
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Adrian Herreradev-arm: GenericTimer, freq as 32-bit value
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Disambuiguate NumFloatV7ArchRegs usage
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Unify VLdmStm behaviour when reg out of index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Fix NumVecV7ArchRegs value (64->16)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Reorder arch/arm/registers.hh constants
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-10 Giacomo Travagliniarch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinitests: AArch64 Linux as quick regressions (instead...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add Request::isMasked to check for byte strobing
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-09 Giacomo Travaglinimem: Add byteEnable copy to Request copy constructor
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-03 Giacomo Travaglinisim-se: Avoid function overloading for syscall implementation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-28 Adrian Herreradev-arm: device name in AmbaFake accesses
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase, python: Allow dirname selection for the interpreter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Add --redirects for syscall emulation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinibase: Fix DPRINTF_UNCONDITIONAL on gem5.fast
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2019-11-27 Giacomo Travagliniconfigs: Add root redirect path in SE mode only when set
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travaglinisim-se: Check Path redirection when mmapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-27 Giacomo Travagliniconfigs: Fix baremetal platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-26 Giacomo Travagliniarch-arm: Make the Tarmac parsed registers case insensitive
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Adrian Herreraarch-arm: default MIDR for Armv8 ISA processors
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-25 Giacomo Travaglinidev-arm: Adjust off_chip ranges in VExpress_GEM5 platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-21 Giacomo Travaglinibase: Remove tests making use of Big/LittleEndianOrder...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Adrian Herreraarch-arm: R/W interface to AArch32 HCR2 misc reg
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix short descriptors cacheability during...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-18 Giacomo Travagliniarch-arm: Fix long descriptors cacheability during...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-14 Giacomo Travaglinitests: Specify a non-default root folder for regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-13 Adrian Herreraarch-arm: fix routeToHyp for AArch64 in faults
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super in arm_generic whenever possible
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Using super for calling superclass __init__
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-12 Giacomo Travaglinitests: Remove Noncoherent cache from regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Fix TarmacParser handling of 64bit LD/ST
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Travagliniarch-arm: Provide SVE support to the TarmacTracer
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-11 Giacomo Gabrielliarch-arm: Provide SVE support to the TarmacParser
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-05 Giacomo Travagliniarch-arm: Annotate original address in CMOs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-05 Adrian Herreradev-arm: optional instantiation of GICv3 ITS
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-01 Adrian Herreraarch-arm: generic method for getting an ArmSystem
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-11-01 Giacomo Travaglinidev-arm: Add SMMUv3 to VExpress_GEM5_V*
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-31 Giacomo Travagliniconfigs: Add baremetal.py example script
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-30 Giacomo Travaglinibase: Name segments after their index
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Clean setupBootLoader signature
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travagliniconfigs: Do not assume bootmem is a System child
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-22 Giacomo Travaglinidev-arm, configs: Using _on_chip_memory for on chip...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Using scoped string in DPRINTFNR
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-16 Giacomo Travaglinibase: Fix gem5.fast compilation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travaglinidev-arm: Carve out a portion of VExpress_GEM5 for the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-15 Giacomo Travagliniconfigs: Add simpleSystem helper to generate devices...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travagliniarch-arm: Move generateDtb to ArmSystem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-10 Giacomo Travaglinidev-arm, configs: Remove RealViewPBX platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Annotate CM flag in AA64 CM Instructions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-03 Giacomo Travagliniarch-arm: Set CM bit in DataAbort
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travaglinisim: Mark System::getThreadContext method as const
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Marc Mari Barcelodev-arm: Improve fault message on SMMUv3 translation...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Marc Mari Barcelodev-arm: Fix address used to update the SMMUv3 Walk...
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-10-02 Giacomo Travagliniarch-arm: Create helper for sending events (SEV)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Conditionally enable HDLcd when doing DTB...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travaglinidev-arm: Add HDLcd DTB autogeneration
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-19 Giacomo Travagliniarch-arm: PSTATE.PAN changes should inval cached regs...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Adrian Herrerasystem-arm: Add ITS node in platforms/vexpress_gem5_v2_base...
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2019-09-18 Giacomo Travagliniarch-arm: Fix Data Abort ISS when caused by Atomic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: ISV bit in DataAbort should check for translation...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-18 Giacomo Travagliniarch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-16 Giacomo Travaglinidev-arm: Allow IOMMU binding to HDLcd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev-arm: Store the IOMMU reference from within the...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-13 Giacomo Travaglinidev: Enable DTB IOMMU binding with a DMA object
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Reset HPPI when clearing an LPI
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Add resetHppi method in the GICv3 cpu interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Cleanup GICv3 initialization
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Initialize GICD_TYPER once at construction...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Writes to IGRPEN1_EL3 triggering update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix GICv3 ITS cmdq wrapping
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-09 Giacomo Travaglinidev-arm: Implement message-based SPIs
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-07 Giacomo Travaglinidev-arm: Add GICD_SGIR register
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev: Enable Terminal output's dump to stdout
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: State update when setting MISCREG_ICC_IGRPENx...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking
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2019-09-06 Giacomo Travaglinidev-arm: Add read/writeBanked helpers to GICv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Add explicit AArch64 MiscReg banking
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Use same template across all MSR inst
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: SySDC64 Instructions (CMO) using MiscRegIndex
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Add GICv3 unimplemented Hyp Active Priorities...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Allow 32-bit access to GITS_TYPER
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Cpu interface groupEnabled check for global...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Check if INTID group is enabled when reading...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Writing GICD_CTLR should trigger an update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Rewrite GICv3 update
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Fix GICv3 IGRPMOD writes
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: SGI registers undecoded in AArch32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travagliniarch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Giacomo Travaglinidev-arm: Fix SGI generation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Adrian Herreradev-arm: Gicv3 ITS device tree autogen
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-06 Adrian Herreradev-arm: modify GICv3 ITS default addr
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-05 Giacomo Travaglinidev-arm: Improper translation slot release in SMMUv3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-05 Jan-Peter Larssondev-arm: Implement invalidateASID in SMMUv3 WalkCache
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-09-05 Adrian Herreradev-arm: Implement invalidateVA/VAA in SMMUv3 WalkCache
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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