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Added blackbox $__COUNT_ cell model
2017-09-01 Andrew ZonenbergAdded blackbox $__COUNT_ cell model
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2017-09-01 Andrew ZonenbergRefactoring: moved modules still in cells_sim to cells_sim_wip
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2017-08-31 Andrew ZonenbergMerge branch 'counter-extraction' of github.com:azonenberg...
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2017-08-31 Andrew Zonenbergextract_counter: Added optimizations to remove unused...
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2017-08-30 Andrew ZonenbergMerge branch 'master' of https://github.com/cliffordwolf...
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2017-08-30 Andrew Zonenbergextract_counter: Minor changes requested to comply...
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2017-08-29 Andrew ZonenbergFinished refactoring counter extraction to be nice...
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2017-08-29 Andrew ZonenbergRefactored extract_counter to be generic vs GreenPAK...
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2017-08-29 Andrew ZonenbergRefactoring: Renamed greenpak4_counters pass to extract_coun...
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2017-08-28 Andrew ZonenbergReformatted GP_COUNTx_ADV resets to avoid Yosys thinking...
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2017-08-27 Andrew ZonenbergFixed bug causing GP_SPI model to not synthesize
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2017-08-15 Andrew ZonenbergFixed more issues with GreenPAK counter sim models
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2017-08-15 Andrew ZonenbergUpdated PGEN model to have level triggered reset (matches...
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2017-08-15 Andrew ZonenbergFixed bug in GP_COUNTx model
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2017-08-15 Andrew ZonenbergFixed bug where GP_COUNTx_ADV would wrap even when...
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2017-08-14 Robert Oucoolrunner2: Add INVERT parameter to some BUFGs
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2017-08-14 Robert Oucoolrunner2: Add FFs with clock enable to cells_sim.v
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2017-08-14 Robert Ouabc: Allow +/ filenames in the abc command
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2017-08-14 Robert Oujson: Parse inout correctly rather than as an output
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2017-08-14 Andrew Zonenbergrmports: Now remove ports from cell instances if we...
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2017-08-14 Andrew ZonenbergProcessModule is no longer virtual (why was it in the...
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2017-08-14 Andrew Zonenbergrmports now works on all modules in the design, not...
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2017-08-14 Andrew ZonenbergUpdated Makefile to reflect opt_rmports being renamed...
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2017-08-14 Andrew ZonenbergRenamed opt_rmports pass to rmports
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2017-08-14 Andrew ZonenbergFixed typo in GP_COUNT8 sim model
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2017-08-14 Andrew ZonenbergFixed typo in error message
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2017-08-14 Andrew ZonenbergChanged LEVEL resets for GP_COUNTx to be properly synthesizeable
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2017-08-14 Andrew ZonenbergChanged LEVEL resets to be edge triggered anyway
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2017-08-14 Andrew ZonenbergAdded level-triggered reset support to GP_COUNTx simulation...
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2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT8_ADV
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2017-08-14 Andrew ZonenbergFixed undeclared "count" in GP_COUNT14_ADV
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2017-08-14 Andrew ZonenbergFixed typo in last commit
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2017-08-14 Andrew ZonenbergFinished initial GP_COUNT8/14/8_ADV/14_ADV sim models...
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2017-08-14 Andrew ZonenbergFixed typo in COUNT8 model
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2017-08-14 Andrew ZonenbergMoved GP_POR out of digital cells b/c it has delays
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2017-08-14 Andrew ZonenbergImproved cells_sim_digital model for GP_COUNT8
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2017-08-14 Andrew ZonenbergRefactored GreenPAK4 cells_sim into cells_sim_ams and...
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2017-08-14 Andrew ZonenbergImproved handling of constant connections in opt_rmports
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2017-08-14 Andrew ZonenbergFixed handling of cell ports that aren't wires
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2017-08-14 Andrew Zonenbergopt_rmports: Fixed incorrect handling of multi-bit...
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2017-08-14 Andrew ZonenbergRemoved commented out debug code
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2017-08-14 Andrew ZonenbergAdded opt_rmports pass (remove unconnected ports from...
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2017-06-24 Andrew Zonenberggreenpak4_counters: Changed generation of primitive...
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2017-05-23 Andrew Zonenberggreenpak4_counters: Added support for parallel output...
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2017-02-24 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-02-16 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-02-14 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-02-11 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-01-15 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-01-05 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-01-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2017-01-01 Andrew Zonenberggreenpak4: Added POUT to GP_COUNTx cells
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2016-12-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2016-12-21 Andrew Zonenberggreenpak4: Added INT pin to GP_SPI
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2016-12-21 Andrew Zonenberggreenpak4: removed unused MISO pin from GP_SPI
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2016-12-20 Andrew Zonenberggreenpak4: Removed SPI_BUFFER parameter
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2016-12-20 Andrew Zonenberggreenpak4: replaced MOSI/MISO with single one-way SDAT pin
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2016-12-20 Andrew Zonenberggreenpak4: Changed port names on GP_SPI for clarity
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2016-12-20 Andrew Zonenberggreenpak4: Initial implementation of GP_SPI cell
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2016-12-17 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2016-12-17 Andrew Zonenberggreenpak4: Updated GP_DCMP cell model
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2016-12-16 Andrew Zonenberggreenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
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2016-12-15 Andrew Zonenberggreenpak4: Initial version of GP_DCMP skeleton (not...
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2016-12-14 Andrew Zonenberggreenpak4: More fixups of GP_DCMPx cells
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2016-12-14 Andrew Zonenberggreenpak4: And another typo :(
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2016-12-14 Andrew Zonenberggreenpak4: Fixed another typo
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2016-12-14 Andrew Zonenberggreenpak4: Fixed typo
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2016-12-14 Andrew Zonenberggreenpak4: Cleaned up trailing spaces in cells_sim
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2016-12-14 Andrew Zonenberggreenpak4: Added GP_DCMPREF / GP_DCMPMUX
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2016-12-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2016-12-11 Andrew ZonenbergAdded GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
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2016-12-10 Andrew Zonenberggreenpak4: Added support for inferred input/output...
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2016-12-10 Andrew Zonenberggreenpak4: Can now techmap inferred D latches (without...
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2016-12-10 Andrew Zonenberggreenpak4: Inverted D latch cells now have nQ instead...
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2016-12-06 Andrew ZonenbergAdded GP_DLATCH and GP_DLATCHI
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2016-12-06 Andrew ZonenbergInitial implementation of techlib support for GreenPAK...
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2016-12-06 Andrew ZonenbergUpdated help text for synth_greenpak4
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2016-10-19 Andrew ZonenbergFixed typo in last commit
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2016-10-19 Andrew Zonenberggreenpak4: Added GP_PGEN cell definition
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2016-10-19 Andrew ZonenbergAdded GLITCH_FILTER parameter to GP_DELAY
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2016-10-19 Andrew Zonenberggreenpak4: added model for GP_EDGEDET block
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2016-10-19 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2016-10-17 Andrew Zonenberggreenpak4: Changed parameters for GP_SYSRESET
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2016-08-14 Andrew Zonenberggreenpak4: Changed name of inverted output ports for...
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2016-08-14 Andrew Zonenberggreenpak4: Added GP_DFFxI cells
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2016-08-14 Andrew Zonenberggreenpak4: Renamed ports for better consistency (see...
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2016-07-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
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2016-07-12 Andrew ZonenbergAdded GP_DAC cell
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2016-07-12 Andrew ZonenbergRemoved VOUT port of GP_BANDGAP
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2016-07-12 Andrew ZonenbergRemoved splitnets in prep for new gp4par parser
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2016-05-08 Andrew ZonenbergAdded GP_DELAY cell
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2016-05-08 Andrew ZonenbergFixed typo in port name
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2016-05-08 Andrew ZonenbergFixed extra semicolon
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2016-05-08 Andrew ZonenbergFixed typo in parameter name
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2016-05-08 Andrew ZonenbergAdded simulation timescale declaration
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2016-05-05 Andrew ZonenbergChanged order of passes for better handling of INIT...
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2016-05-05 Andrew ZonenbergChanged port names in greenpak shregmap
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2016-05-05 Andrew ZonenbergRenamed module parameter
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2016-05-04 Andrew ZonenbergRefactored synth_greenpak4 to use iopadmap for mapping...
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