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Missing doc for -tech xilinx in shregmap
2019-04-03
Eddie Hung
-nosrl meant when -nobram
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2019-04-03
Eddie Hung
Remove duplicate STARTUPE2
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2019-04-03
Eddie Hung
Disable shregmap in synth_xilinx if -retime
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2019-04-03
Eddie Hung
Add changelog entry
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-25
Eddie Hung
synth_xilinx to use shregmap with -minlen 3
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2019-03-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-25
Eddie Hung
Create one $shiftx per bit in width
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2019-03-23
Eddie Hung
Add a pmux-to-shiftx optimisation to proc_mux
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2019-03-23
Eddie Hung
Cope with SHREG not having E port; Revert $pmux fine...
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2019-03-23
Eddie Hung
Add support for SHREGMAP+$mux, also fine tune $pmux
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2019-03-23
Eddie Hung
Leftover printf
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2019-03-23
Eddie Hung
Fixes for multibit
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2019-03-23
Eddie Hung
Working for 1 bit
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2019-03-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-21
Eddie Hung
Add '-nosrl' option to synth_xilinx
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2019-03-21
Eddie Hung
Opt
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2019-03-20
Eddie Hung
Fix spacing
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2019-03-20
Eddie Hung
Fine tune cells_map.v
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2019-03-20
Eddie Hung
Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable...
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2019-03-20
Eddie Hung
Add support for variable length Xilinx SRL > 128
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2019-03-19
Eddie Hung
Restore original synth_xilinx commands
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2019-03-19
Eddie Hung
Fix spacing
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2019-03-19
Eddie Hung
shregmap -tech xilinx to delete $shiftx for var length SRL
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2019-03-19
Eddie Hung
Fix INIT for variable length SRs that have been bumped...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Make output port a non chain user
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-19
Eddie Hung
Add author name
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2019-03-18
Eddie Hung
Fix shregmap to correctly recognise non chain users...
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2019-03-18
Eddie Hung
shiftx NULL pointer check
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2019-03-16
Eddie Hung
Cleanup
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2019-03-16
Eddie Hung
Only accept <128 for variable length, only if $shiftx...
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2019-03-16
Eddie Hung
Cleanup synth_xilinx
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2019-03-16
Eddie Hung
Working
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2019-03-14
Eddie Hung
Reverse bits in INIT parameter for Xilinx, since MSB...
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2019-03-14
Eddie Hung
Misspell
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2019-03-14
Eddie Hung
Revert "Add shregmap -init_msb_first and use in synth_xilinx"
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14
Eddie Hung
Add shregmap -init_msb_first and use in synth_xilinx
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2019-03-14
Eddie Hung
Fix cells_map for SRL
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2019-03-14
Eddie Hung
Move shregmap until after first techmap
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2019-03-13
Eddie Hung
Refactor $__SHREG__ in cells_map.v
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2019-03-09
Eddie Hung
Update help message for -chparam
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2019-03-09
Eddie Hung
Add -chparam option to verific command
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2019-03-09
Eddie Hung
Fix spelling
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2019-02-28
Eddie Hung
Remove SRL16/32 from cells_xtra
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2019-02-28
Eddie Hung
Add SRL16 and SRL32 sim models
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2019-02-28
Eddie Hung
Fix SRL16/32 techmap off-by-one
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2019-02-28
Eddie Hung
synth_xilinx to call shregmap with enable support
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2019-02-28
Eddie Hung
synth_xilinx to use shregmap with -params too
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2019-02-28
Eddie Hung
synth_xilinx to now have shregmap call after dff2dffe
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2019-02-28
Eddie Hung
Add techmap rule for $__SHREG_DFF_P_ to SRL16/32
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2019-02-21
Eddie Hung
Revert "Add -B option to autotest.sh to append to backend_opts"
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2019-02-20
Eddie Hung
Remove simple_defparam tests
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2019-02-19
Eddie Hung
Add aiger tests to make tests
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2019-02-19
Eddie Hung
Merge branch 'master' into read_aiger
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2019-02-19
Eddie Hung
Fix for using POSIX basename
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2019-02-18
Eddie Hung
Missing OSX headers?
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2019-02-18
Eddie Hung
Revert "Missing headers for Xcode?"
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2019-02-18
Eddie Hung
Merge branch 'dff_init' into read_aiger
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2019-02-17
Eddie Hung
Instead of INIT param on cells, use initial statement...
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2019-02-17
Eddie Hung
Revert "Add INIT parameter to all ff/latch cells"
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2019-02-17
Eddie Hung
read_aiger to ignore line after ands for ascii, not...
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2019-02-17
Eddie Hung
One more merge conflict
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2019-02-17
Eddie Hung
Merge branch 'dff_init' into read_aiger
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-02-12
Eddie Hung
Missing headers for Xcode?
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2019-02-12
Eddie Hung
Merge branch 'read_aiger' of github.com:eddiehung/yosys...
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2019-02-12
Eddie Hung
Use module->add{Not,And}Gate() functions
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2019-02-11
Eddie Hung
Do not break for constraints
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2019-02-11
Eddie Hung
No increment line_count for binary ANDs
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2019-02-11
Eddie Hung
Do not ignore newline after AND in binary AIG
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2019-02-08
Eddie Hung
Merge remote-tracking branch 'origin/dff_init' into...
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2019-02-08
Eddie Hung
addDff -> addDffGate as per @daveshah1
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2019-02-08
Eddie Hung
Fix tabulation
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2019-02-08
Eddie Hung
-module_name arg to go before -clk_name
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2019-02-08
Eddie Hung
Support and differentiate between ASCII and binary...
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2019-02-08
Eddie Hung
Add missing "[options]" to read_blif help
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2019-02-08
Eddie Hung
Allow module name to be determined by argument too
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2019-02-08
Eddie Hung
Refactor into AigerReader class
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2019-02-08
Eddie Hung
Parse binary AIG files
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2019-02-08
Eddie Hung
Add binary AIGs converted from AAG
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2019-02-08
Eddie Hung
Refactor to parse_aiger_header()
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2019-02-08
Eddie Hung
Add comment
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2019-02-08
Eddie Hung
Handle reset logic in latches
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2019-02-08
Eddie Hung
Change literal vars from int to unsigned
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2019-02-08
Eddie Hung
Create clk outside of latch loop
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2019-02-08
Eddie Hung
Handle latch symbols too
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2019-02-08
Eddie Hung
Remove return after log_error
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2019-02-08
Eddie Hung
Add support for symbol tables
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2019-02-08
Eddie Hung
Stub for binary AIGER
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2019-02-06
Eddie Hung
Cope WIDTH of ff/latch cells is default of zero
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
Remove check for cell->name[0] == '$'
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2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
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2019-02-06
Eddie Hung
Revert most of autotest.sh; for non *.v use Yosys to...
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2019-02-06
Eddie Hung
Refactor
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2019-02-06
Eddie Hung
write_verilog to cope with init attr on q when -noexpr
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