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Reformat sim_console
2019-09-19 Anton BlanchardReformat sim_console
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2019-09-19 Anton BlanchardReformat multiply_tb
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2019-09-19 Anton BlanchardReformat execute2
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2019-09-19 Anton BlanchardReformat CR file
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2019-09-19 Anton BlanchardReformat register file
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2019-09-16 Anton BlanchardMove byte reversal of stores to first cycle
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2019-09-16 Anton Blanchardexecute1 no longer needs sim_console
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2019-09-15 Anton BlanchardFix multiply_tb
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2019-09-15 Anton BlanchardAdd an icache testbench
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2019-09-15 Anton BlanchardRemove cycle in writeback
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2019-09-15 Anton BlanchardFix make check
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2019-09-15 Anton BlanchardFix spurious outstanding assert
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2019-09-15 Anton BlanchardAdd a decode for the nop instruction
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2019-09-15 Anton BlanchardAdd a default value for RESET_ADDRESS
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2019-09-14 Anton BlanchardReformat writeback.vhdl
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2019-09-14 Anton BlanchardExit if we try to write more than one GPR or CR in...
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2019-09-12 Anton BlanchardNo need to gate nia or insn in decode1
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2019-09-12 Anton BlanchardAdd a simple direct mapped icache
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2019-09-12 Anton BlanchardSOC memory wishbone should clear ACK regardless of STB
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2019-09-12 Anton BlanchardFix clk_gen_bypass
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2019-09-11 Anton BlanchardExplicitly check against '1' in if statements
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2019-09-11 Anton BlanchardRemove names from end record statements
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2019-09-11 Anton BlanchardFix issue in loadstore1
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2019-09-11 Anton BlanchardFix issue in execute2
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2019-09-11 Anton BlanchardRemove nia from loadstore and multiply
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2019-09-11 Anton BlanchardReformat core.vhdl
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2019-09-11 Anton BlanchardRemove sim console
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2019-09-11 Anton BlanchardReduce multiply to 2 cycles
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2019-09-11 Anton BlanchardRegister outputs on writeback
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2019-09-11 Anton BlanchardRegister outputs on execute2
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2019-09-11 Anton BlanchardRegister outputs on loadstore1
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2019-09-11 Anton BlanchardMove debug execute output into decode2
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2019-09-11 Anton BlanchardRework pipeline, add stall and flush signals
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2019-09-10 Anton BlanchardUpdate Makefile dependencies
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2019-09-10 Anton BlanchardDon't send out X state from the memory behavioural
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2019-09-10 Anton BlanchardQuieten multiply warning
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2019-09-09 Anton BlanchardSimplify multiply
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2019-09-09 Anton BlanchardAdd a decode bit to mark an instruction as single through...
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2019-09-09 Benjamin Herrenschmidtdecode1 array fix header
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2019-09-09 Benjamin HerrenschmidtUse simulated UART in core test bench
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2019-09-09 Benjamin HerrenschmidtMake sim poll non-blocking
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2019-09-09 Benjamin HerrenschmidtAdd simulated UART design
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2019-09-09 Anton BlanchardFix CR forwarding
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2019-09-09 Anton BlanchardAdd forwarding in the register file
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2019-09-09 Anton BlanchardMore second write port removal
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2019-09-09 Anton BlanchardAdd some assertions to writeback
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2019-09-09 Anton BlanchardRemove second write port
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2019-09-09 Anton BlanchardRemove some more loadstore debug
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2019-09-09 Anton BlanchardFix issues with CR rework
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2019-09-09 Anton BlanchardSilence some loadstore related debug
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2019-09-09 Anton BlanchardClean up register read debug output
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2019-09-09 Anton BlanchardRework CR file and add forwarding
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2019-09-08 Anton BlanchardCmod A7-35 support
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2019-09-08 Anton BlanchardStores need to wait for wishbone write ack
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2019-09-07 Anton BlanchardAdd CONFIG_VOLTAGE and CFGBVS entries
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2019-09-07 Anton BlanchardRework SOC reset
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2019-09-07 Anton BlanchardRename a few reset signals
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2019-09-05 Anton BlanchardUse a better input signal in writeback
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2019-09-03 Anton BlanchardRework decode2
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2019-08-29 Anton BlanchardArty A7 reset pin is C2
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2019-08-29 Anton BlanchardA few Travis CI fixes
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2019-08-28 Anton BlanchardAdd an initial travis.yml
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2019-08-28 Anton BlanchardAdd srd and srw
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2019-08-28 Anton BlanchardAdd sim only divw
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2019-08-27 Anton BlanchardFix ghdl build error with pp_soc_memory
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2019-08-27 Anton Blanchardmicropython only requires 512kB of BRAM
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2019-08-27 Anton BlanchardAdd -Wall to CFLAGS
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2019-08-26 Anton BlanchardAdd missing argument to fprintf warning
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2019-08-26 Anton BlanchardAdd some initial FPGA synthesis instructions
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2019-08-26 Anton BlanchardRebuild hello world assuming a 50MHz clock
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2019-08-23 Anton BlanchardAdd a simple hello_world example that also echos input
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2019-08-23 Anton BlanchardAdd a few more FPGA related files
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2019-08-22 Anton BlanchardInitial import of microwatt
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