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fhdl.ir: remove iter_domains().
2018-12-13 whitequarkfhdl.ir: remove iter_domains().
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2018-12-13 whitequarkfhdl: cd_name→domain.
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2018-12-13 whitequarkfhdl.cd: add tests.
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2018-12-13 whitequarkfhdl.xfrm: implement DomainRenamer.
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2018-12-13 whitequarkfhdl.xfrm: add test for ControlInserter with subfragments.
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2018-12-13 whitequarkfhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 whitequarkfhdl.ir: add tests for port propagation.
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2018-12-13 whitequarkSet up Travis CI.
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2018-12-13 whitequarkAdd LICENSE.
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2018-12-13 whitequarksetup: check Python version.
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2018-12-13 whitequarkfhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 whitequarkfhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 whitequarkfhdl.dsl: add tests for submodules.
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2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level...
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2018-12-13 whitequarkfhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 whitequarkfhdl.ast: fix Switch._?hs_signals() for switch without...
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2018-12-13 whitequarkback.verilog: detect undriven public wires using Yosys.
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2018-12-13 whitequarkback.rtlil: fix swapped operands in sync assign.
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2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion.
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2018-12-13 whitequarkback.rtlil: explicitly set the top module.
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2018-12-13 whitequarkfhdl.ir: explain how port enumeration works.
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2018-12-13 whitequarkback.rtlil: explain how RTLIL conversion works.
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2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear...
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2018-12-13 whitequarkback.rtlil: give clocks and resets nicer names.
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2018-12-13 whitequarkcompat.fhdl.module: implement finalization.
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2018-12-13 whitequarkback.rtlil: match shape of $mux ports A/B/Y.
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2018-12-13 whitequarktracer: add support for Python 3.7.
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2018-12-13 whitequarkfhdl.ast: bits_sign→shape.
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2018-12-13 whitequarkfhdl.ast: add tests for most logic.
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2018-12-13 whitequarkMeasure test coverage.
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2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code...
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2018-12-12 whitequarkcompat.fhdl.bitcontainer: import/wrap Migen code.
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2018-12-12 whitequarkfhdl.ast.Signal: implement .like().
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2018-12-12 whitequarkfhdl.ir: fix port threading code.
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2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 whitequarkfhdl.ast.Signal: fix typo.
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2018-12-12 whitequarkfhdl.ast.Signal: implement attrs field.
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2018-12-12 whitequarkgenlib.cdc.MultiReg: self.regs should be a private...
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2018-12-12 whitequarkfhdl.ast.Signal: implement width derivation from min...
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2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen.
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2018-12-12 whitequarkfhdl.ast.Signal: implement reset_less signals.
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2018-12-12 whitequarkfhdl.ast.Signal: assign an internal name if tracer...
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2018-12-12 whitequarkfhdl.dsl: allow f.sync["dom"] as a synonym of f.sync...
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2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInserter.
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2018-12-12 whitequarkInitial commit.
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