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begin working on linux verilator simulation
2022-04-13
Tobias Platen
begin working on linux verilator simulation
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2022-04-12
Tobias Platen
revert changes in wishbone_bram_wrapper.vhdl
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2022-04-12
Tobias Platen
cleanup Makefile
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2022-04-04
Tobias Platen
correct wishbone data directions
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2022-04-03
Tobias Platen
ram addr calculation ram_addr
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2022-04-03
Tobias Platen
more backporting work
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2022-04-03
Tobias Platen
backport wishbone_bram_wrapper changes
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2022-04-02
Tobias Platen
wire out signals needed for verilator simulation
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2022-04-01
Tobias Platen
fpga/top-orangecrab0.2.vhdl: -gEXTERNAL_CORE now works
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2022-03-31
Tobias Platen
building microwatt-verilator with external core now...
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2022-03-30
Tobias Platen
add external core option
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2022-03-30
Tobias Platen
begin merge of soc.vhdl, fix Makefile
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2022-03-28
Tobias Platen
add read_verilog when using external core
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2022-03-27
Tobias Platen
more work on verilator backport
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2022-03-27
Tobias Platen
begin verilator_trace backport
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2022-03-24
Tobias Platen
try using plru_dummy.vhdl
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2022-03-23
Tobias Platen
partial synthesize with EXTERNAL_CORE
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2022-03-23
Tobias Platen
allow using external core
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2022-03-22
Tobias Platen
Merge remote-tracking branch 'to-be-merged/merge-3d...
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