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yosys.git
2013-08-19
Clifford Wolf
Fixed width and sign detection for ** operator
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2013-08-19
Clifford Wolf
Added support for bufif0/bufif1 primitives
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2013-08-19
Clifford Wolf
Improved ast dumping (ast/verilog frontend)
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2013-08-15
Clifford Wolf
Implemented same div-by-zero behavior as found in other...
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2013-08-15
Clifford Wolf
Fixed signed div/mod in const eval (rounding and stuff)
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2013-08-15
Clifford Wolf
Added ezsat api for creation of anonymous vectors
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2013-08-15
Clifford Wolf
Added sat -ignore_div_by_zero switch
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2013-08-15
Clifford Wolf
Added eval -brute_force_equiv_checker_x mode
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2013-08-12
Clifford Wolf
Added support for "2**n" shifter encoding
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2013-08-11
Clifford Wolf
Added SAT support for $div and $mod cells
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2013-08-11
Clifford Wolf
Added "clean -purge" and ";;;" support
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2013-08-11
Clifford Wolf
Added ";;" as shortcut for "; clean;"
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2013-08-10
Clifford Wolf
freduce performance fix
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2013-08-09
Clifford Wolf
Added $div and $mod technology mapping
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2013-08-09
Clifford Wolf
Added techmap -opt mode
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2013-08-09
Clifford Wolf
Some fixes to improve determinism
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2013-08-08
Clifford Wolf
Sort ctrl signals in fsm_extract
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2013-08-08
Clifford Wolf
Added -try option to freduce pass
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2013-08-08
Clifford Wolf
Added "clean" command (less verbose opt_clean)
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2013-08-07
Clifford Wolf
Fixed topological ordering in freduce pass
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2013-08-07
Clifford Wolf
Improved handling of private names in opt_clean and...
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2013-08-07
Clifford Wolf
Added stubnets example to manual prog chapter
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2013-08-06
Clifford Wolf
Small bugfixes in freduce pass
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2013-08-06
Clifford Wolf
Added freduce command
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2013-08-06
Clifford Wolf
Fixed SigPool::del() method
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2013-08-06
Clifford Wolf
Added proper deallocation of history buffer
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2013-08-01
Clifford Wolf
Updated TODO section in README
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2013-07-27
Clifford Wolf
Added "design" command (-reset, -save, -load)
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2013-07-25
Clifford Wolf
Added "help -write-web-command-reference-manual"
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2013-07-25
Clifford Wolf
Fixed comments in manual rtlil/ilang syntax
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2013-07-25
Clifford Wolf
Added RTLIL and Liberty syntax highlighting to manual
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2013-07-24
Clifford Wolf
Automatically run "proc" on extract map files
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2013-07-23
Clifford Wolf
Added $lut cells and abc lut mapping support
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2013-07-23
Clifford Wolf
Fixed "make clean" for manual files
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2013-07-21
Clifford Wolf
Added web site link to README
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2013-07-20
Clifford Wolf
Added Yosys Manual
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2013-07-12
Clifford Wolf
More fixes in ternary op sign handling
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2013-07-11
Clifford Wolf
Fixed sign handling in ternary operator
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2013-07-11
Clifford Wolf
Added ast frontend refactoring to TODO
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2013-07-11
Clifford Wolf
Another vloghammer related bugfix
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2013-07-10
Clifford Wolf
Bugfixes for empty signal vectors
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2013-07-09
Clifford Wolf
Fixed sign propagation in bit-wise operators
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2013-07-09
Clifford Wolf
More fixes in ast expression sign/width handling
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2013-07-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-07-09
Clifford Wolf
Fixed shift ops with large right hand side
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2013-07-09
Clifford Wolf
Major redesign of expr width/sign detecion (verilog...
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2013-07-07
Clifford Wolf
Fixed another bug found using vloghammer
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2013-07-07
Clifford Wolf
Fixed AST_CONSTANT node generation
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2013-07-07
Clifford Wolf
Removed tests/xsthammer
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2013-07-07
Clifford Wolf
Added opt_clean -purge option
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2013-07-07
Clifford Wolf
Fixed handling of $eq and $ne in opt_const
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2013-07-05
Clifford Wolf
Fixed vivado related xsthammer bugs
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2013-07-05
Clifford Wolf
Various improvements in xsthammer report generator
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2013-07-05
Clifford Wolf
Added work-around to isim bug in xsthammer report script
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2013-07-05
Clifford Wolf
Fixed gcc warnings in ezminisat
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2013-07-05
Clifford Wolf
Added CARRY4 Xilinx cell to xsthammer cell lib
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2013-07-05
Clifford Wolf
Added xsthammer report generator
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2013-07-04
Clifford Wolf
Improved xsthammer quartus support
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2013-07-04
Clifford Wolf
Added Altera Cyclon III cell library to xsthammer
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2013-07-04
Clifford Wolf
Documentation updates
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2013-07-04
Clifford Wolf
Added defparam support to Verilog/AST frontend
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2013-07-03
Clifford Wolf
Added QMAKE makefile variable
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2013-07-03
Clifford Wolf
Added Altera Quartus support to xsthammer
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2013-07-03
Clifford Wolf
Progress in xsthammer
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2013-06-26
Clifford Wolf
Added vivado support to xsthammer
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2013-06-23
Clifford Wolf
Added SAT support for -all/-max with -verify
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2013-06-20
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-06-20
Clifford Wolf
Added timout functionality to SAT solver
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2013-06-19
Clifford Wolf
Added renaming of wires and cells to "rename" command
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2013-06-19
Clifford Wolf
Added "eval" pass
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2013-06-18
Clifford Wolf
Fixed build with clang
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2013-06-18
Clifford Wolf
Added splitnets command
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2013-06-18
Clifford Wolf
Added RTLIL::Module::fixup_ports() API and RTLIL::...
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2013-06-17
Clifford Wolf
Added more stuff to xsthammer, found first xst bug
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2013-06-15
Clifford Wolf
Added support for "assign" statements in abc vlparse
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2013-06-15
Clifford Wolf
Added ternary op and concat op to xsthammer
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2013-06-14
Clifford Wolf
Fixed even more ConstEval bugs found using xsthammer
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2013-06-13
Clifford Wolf
Added consteval testing to xsthammer and fixed bugs
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2013-06-13
Clifford Wolf
More xsthammer improvements (using xst 14.5 now)
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2013-06-13
Clifford Wolf
More fixes for bugs found using xsthammer
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2013-06-12
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-06-12
Clifford Wolf
Another fix for a bug found using xsthammer
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2013-06-12
Clifford Wolf
Added "scatter" command
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2013-06-12
Clifford Wolf
Renamed yosys-show temp files to be dot-files in the...
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2013-06-12
Clifford Wolf
Fixed gcc build (c++11 stuff in ezSAT)
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2013-06-11
Clifford Wolf
Further improved and extended xsthammer
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2013-06-10
Clifford Wolf
More xsthammer improvements
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2013-06-10
Clifford Wolf
More sign-extension related fixes
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2013-06-10
Clifford Wolf
Sign-extension related fixes in SatGen and AST frontend
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2013-06-10
Clifford Wolf
Progress xsthammer scripts
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2013-06-10
Clifford Wolf
Improvements and fixes in SAT code
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2013-06-10
Clifford Wolf
Added history file read/write to driver
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2013-06-10
Clifford Wolf
Progress in xsthammer: working proof for cell models
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2013-06-10
Clifford Wolf
Fixes and improvements in AST const folding
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2013-06-10
Clifford Wolf
Enabled AST/Verilog front-end optimizations per default
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2013-06-10
Clifford Wolf
Fixed generation of newlines in "dump" output
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2013-06-10
Clifford Wolf
Added "rename" command
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2013-06-10
Clifford Wolf
Progress on xsthammer
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2013-06-09
Clifford Wolf
Added first xsthammer scripts
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2013-06-09
Clifford Wolf
Renamed "sat_solve" pass to "sat"
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