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yosys.git
2014-08-05
Clifford Wolf
Fixed AST handling of variables declared inside a funct...
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2014-08-04
Clifford Wolf
Added "show -signed"
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2014-08-04
Clifford Wolf
Added support for non-standard "module mod_name(.....
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2014-08-04
Clifford Wolf
Added RTLIL::IdString::in(...)
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2014-08-03
Clifford Wolf
Fixed "share" for memory read ports
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2014-08-03
Clifford Wolf
Added "wreduce" to some of the standard test benches
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2014-08-03
Clifford Wolf
Progress in "wreduce" pass
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2014-08-03
Clifford Wolf
Added "wreduce" command (work in progress)
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2014-08-03
Clifford Wolf
Added query() API to ModIndex
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2014-08-03
Clifford Wolf
Added ID() macro for static IdStrings
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2014-08-03
Clifford Wolf
Implemented recursive techmap
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2014-08-03
Clifford Wolf
Fixes in show command (related to new IdString)
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2014-08-02
Clifford Wolf
Implemented simplemap support for "techmap -extern"
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2014-08-02
Clifford Wolf
Fixed a va_list corruption in logv_error()
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2014-08-02
Clifford Wolf
Be more conservative with printing decimal numbers...
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2014-08-02
Clifford Wolf
Improved verilog output for ordinary $mux cells
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2014-08-02
Clifford Wolf
Bugfix in "techmap -extern"
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2014-08-02
Clifford Wolf
Removed at() method from RTLIL::IdString
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2014-08-02
Clifford Wolf
No implicit conversion from IdString to anything else
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2014-08-02
Clifford Wolf
More bugfixes related to new RTLIL::IdString
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2014-08-02
Clifford Wolf
Limit size of log_signal buffer to 100 elements
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2014-08-02
Clifford Wolf
Improvements in new RTLIL::IdString implementation
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2014-08-02
Clifford Wolf
Fixed a performance bug in opt_reduce
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2014-08-02
Clifford Wolf
Implemented new reference counting RTLIL::IdString
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2014-08-02
Clifford Wolf
Fixed memory corruption related to id2cstr()
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2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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2014-08-01
Clifford Wolf
Preparations for RTLIL::IdString redesign: cleanup...
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2014-08-01
Clifford Wolf
Added logfile hash to statistics footer
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2014-08-01
Clifford Wolf
Replaced sha1 implementation
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2014-08-01
Clifford Wolf
Added per-pass cpu usage statistics
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2014-08-01
Clifford Wolf
Added ModIndex helper class, some changes to RTLIL...
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2014-08-01
Clifford Wolf
Packed SigBit::data and SigBit::offset in a union
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2014-08-01
Clifford Wolf
Consolidated hana test benches into fewer files
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2014-08-01
Clifford Wolf
Added "test_autotb -n <num_iter>" option
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2014-07-31
Clifford Wolf
Renamed modwalker.h to modtools.h
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2014-07-31
Clifford Wolf
Various cleanups in Makefile, Renamed default configura...
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2014-07-31
Clifford Wolf
Added compiler + compiler version + compiler flags...
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2014-07-31
Clifford Wolf
Fixed build of verific bindings
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Added "trace" command
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2014-07-31
Clifford Wolf
Added RTLIL::Monitor
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2014-07-31
Clifford Wolf
Added module->design and cell->module, wire->module...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-31
Clifford Wolf
Renamed "stdcells.v" to "techmap.v"
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2014-07-31
Clifford Wolf
Added "techmap -assert"
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2014-07-31
Clifford Wolf
Reorganized stdcells.v (no actual code change, just...
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2014-07-30
Clifford Wolf
Added "yosys -A"
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2014-07-30
Clifford Wolf
Added "yosys -Q"
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2014-07-30
Clifford Wolf
Added techmap CONSTMAP feature
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2014-07-30
Clifford Wolf
Fixed counting verilog line numbers for "// synopsys...
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2014-07-30
Clifford Wolf
Added write_file command
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2014-07-30
Clifford Wolf
Added "make -j{N}" support to "make test"
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2014-07-30
Clifford Wolf
Improvements in test_cell
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2014-07-30
Clifford Wolf
New techmap default rules for $shr $sshr $shl $sshl
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2014-07-30
Clifford Wolf
Using native ezSAT shift ops in satgen, fixed $shift...
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2014-07-30
Clifford Wolf
Added native support for shift operations to ezSAT
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2014-07-30
Clifford Wolf
Added "log_dump_val_worker(char *v)"
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2014-07-30
Clifford Wolf
Added CodingStyle document
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2014-07-30
Clifford Wolf
Added "kernel/yosys.h" and "kernel/yosys.cc"
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2014-07-29
Clifford Wolf
Added "test_cell" command
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2014-07-29
Clifford Wolf
Renamed "write_autotest" to "test_autotb" and moved...
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2014-07-29
Clifford Wolf
Fixed Verilog pre-processor for files with no trailing...
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2014-07-29
Clifford Wolf
Bugfix in simlib.v for iverilog
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2014-07-29
Clifford Wolf
Allow "hierarchy -generate" for $__ cells
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2014-07-29
Clifford Wolf
Added "techmap -map %{design-name}"
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2014-07-29
Clifford Wolf
Added $shift and $shiftx cell types (needed for correct...
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2014-07-28
Clifford Wolf
Removed left over debug code
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2014-07-28
Clifford Wolf
Fixed part selects of parameters
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2014-07-28
Clifford Wolf
Set results of out-of-bounds static bit/part select...
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2014-07-28
Clifford Wolf
Fixed RTLIL code generator for part select of parameter
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2014-07-28
Clifford Wolf
Fixed width detection for part selects
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2014-07-28
Clifford Wolf
Added support for "upto" wires to Verilog front- and...
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2014-07-28
Clifford Wolf
Added wire->upto flag for signals such as "wire [0...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-28
Clifford Wolf
Added std::initializer_list<> constructor to SigSpec
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2014-07-28
Clifford Wolf
Added cover() to all SigSpec constructors
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2014-07-28
Clifford Wolf
Fixed signdness detection of expressions with bit-...
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2014-07-28
Clifford Wolf
Improvements in tests/vloghtb
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2014-07-27
Clifford Wolf
Added techmap -extern
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2014-07-27
Clifford Wolf
Added proper Design->addModule interface
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2014-07-27
Clifford Wolf
Added topological sorting to techmap
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2014-07-27
Clifford Wolf
Added SigPool::check(bit)
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2014-07-27
Clifford Wolf
Small improvements in PerformanceTimer API
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2014-07-27
Clifford Wolf
Fixed bug in opt_clean
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2014-07-27
Clifford Wolf
Improved performance of opt_const on large modules
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2014-07-27
Clifford Wolf
Added RTLIL::SigSpec::remove_const() handling of packed...
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2014-07-27
Clifford Wolf
Added RTLIL::SigSpecConstIterator
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2014-07-27
Clifford Wolf
Fixed a bug in opt_clean and some RTLIL API usage cleanups
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2014-07-27
Clifford Wolf
Added log_cmd_error_expection
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2014-07-27
Clifford Wolf
Fixed verific bindings for new RTLIL api
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2014-07-27
Clifford Wolf
Fixed ilang parser for new RTLIL API
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2014-07-27
Clifford Wolf
Using new obj iterator API in a few places
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2014-07-27
Clifford Wolf
Added RTLIL::Module::wire(id) and cell(id) lookup functions
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2014-07-27
Clifford Wolf
Added RTLIL::Design::modules()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27
Clifford Wolf
Added conversion from ObjRange to std::vector and std...
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2014-07-27
Clifford Wolf
Added RTLIL::ObjIterator and RTLIL::ObjRange
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2014-07-27
Clifford Wolf
Using std::move() in SigSpec move constructor
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2014-07-27
Clifford Wolf
Added RTLIL::SigSpec move constructor and move assignme...
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2014-07-27
Clifford Wolf
Mostly cosmetic changes to rtlil.h
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