projects / yosys.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
yosys.git
2014-08-03 Clifford WolfImplemented recursive techmap commit | commitdiff | tree
2014-08-03 Clifford WolfFixes in show command (related to new IdString) commit | commitdiff | tree
2014-08-02 Clifford WolfImplemented simplemap support for "techmap -extern" commit | commitdiff | tree
2014-08-02 Clifford WolfFixed a va_list corruption in logv_error() commit | commitdiff | tree
2014-08-02 Clifford WolfBe more conservative with printing decimal numbers... commit | commitdiff | tree
2014-08-02 Clifford WolfImproved verilog output for ordinary $mux cells commit | commitdiff | tree
2014-08-02 Clifford WolfBugfix in "techmap -extern" commit | commitdiff | tree
2014-08-02 Clifford WolfRemoved at() method from RTLIL::IdString commit | commitdiff | tree
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else commit | commitdiff | tree
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString commit | commitdiff | tree
2014-08-02 Clifford WolfLimit size of log_signal buffer to 100 elements commit | commitdiff | tree
2014-08-02 Clifford WolfImprovements in new RTLIL::IdString implementation commit | commitdiff | tree
2014-08-02 Clifford WolfFixed a performance bug in opt_reduce commit | commitdiff | tree
2014-08-02 Clifford WolfImplemented new reference counting RTLIL::IdString commit | commitdiff | tree
2014-08-02 Clifford WolfFixed memory corruption related to id2cstr() commit | commitdiff | tree
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage commit | commitdiff | tree
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup... commit | commitdiff | tree
2014-08-01 Clifford WolfAdded logfile hash to statistics footer commit | commitdiff | tree
2014-08-01 Clifford WolfReplaced sha1 implementation commit | commitdiff | tree
2014-08-01 Clifford WolfAdded per-pass cpu usage statistics commit | commitdiff | tree
2014-08-01 Clifford WolfAdded ModIndex helper class, some changes to RTLIL... commit | commitdiff | tree
2014-08-01 Clifford WolfPacked SigBit::data and SigBit::offset in a union commit | commitdiff | tree
2014-08-01 Clifford WolfConsolidated hana test benches into fewer files commit | commitdiff | tree
2014-08-01 Clifford WolfAdded "test_autotb -n <num_iter>" option commit | commitdiff | tree
2014-07-31 Clifford WolfRenamed modwalker.h to modtools.h commit | commitdiff | tree
2014-07-31 Clifford WolfVarious cleanups in Makefile, Renamed default configura... commit | commitdiff | tree
2014-07-31 Clifford WolfAdded compiler + compiler version + compiler flags... commit | commitdiff | tree
2014-07-31 Clifford WolfFixed build of verific bindings commit | commitdiff | tree
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added... commit | commitdiff | tree
2014-07-31 Clifford WolfAdded "trace" command commit | commitdiff | tree
2014-07-31 Clifford WolfAdded RTLIL::Monitor commit | commitdiff | tree
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module... commit | commitdiff | tree
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys... commit | commitdiff | tree
2014-07-31 Clifford WolfRenamed "stdcells.v" to "techmap.v" commit | commitdiff | tree
2014-07-31 Clifford WolfAdded "techmap -assert" commit | commitdiff | tree
2014-07-31 Clifford WolfReorganized stdcells.v (no actual code change, just... commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "yosys -A" commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "yosys -Q" commit | commitdiff | tree
2014-07-30 Clifford WolfAdded techmap CONSTMAP feature commit | commitdiff | tree
2014-07-30 Clifford WolfFixed counting verilog line numbers for "// synopsys... commit | commitdiff | tree
2014-07-30 Clifford WolfAdded write_file command commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "make -j{N}" support to "make test" commit | commitdiff | tree
2014-07-30 Clifford WolfImprovements in test_cell commit | commitdiff | tree
2014-07-30 Clifford WolfNew techmap default rules for $shr $sshr $shl $sshl commit | commitdiff | tree
2014-07-30 Clifford WolfUsing native ezSAT shift ops in satgen, fixed $shift... commit | commitdiff | tree
2014-07-30 Clifford WolfAdded native support for shift operations to ezSAT commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "log_dump_val_worker(char *v)" commit | commitdiff | tree
2014-07-30 Clifford WolfAdded CodingStyle document commit | commitdiff | tree
2014-07-30 Clifford WolfAdded "kernel/yosys.h" and "kernel/yosys.cc" commit | commitdiff | tree
2014-07-29 Clifford WolfAdded "test_cell" command commit | commitdiff | tree
2014-07-29 Clifford WolfRenamed "write_autotest" to "test_autotb" and moved... commit | commitdiff | tree
2014-07-29 Clifford WolfFixed Verilog pre-processor for files with no trailing... commit | commitdiff | tree
2014-07-29 Clifford WolfBugfix in simlib.v for iverilog commit | commitdiff | tree
2014-07-29 Clifford WolfAllow "hierarchy -generate" for $__ cells commit | commitdiff | tree
2014-07-29 Clifford WolfAdded "techmap -map %{design-name}" commit | commitdiff | tree
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct... commit | commitdiff | tree
2014-07-28 Clifford WolfRemoved left over debug code commit | commitdiff | tree
2014-07-28 Clifford WolfFixed part selects of parameters commit | commitdiff | tree
2014-07-28 Clifford WolfSet results of out-of-bounds static bit/part select... commit | commitdiff | tree
2014-07-28 Clifford WolfFixed RTLIL code generator for part select of parameter commit | commitdiff | tree
2014-07-28 Clifford WolfFixed width detection for part selects commit | commitdiff | tree
2014-07-28 Clifford WolfAdded support for "upto" wires to Verilog front- and... commit | commitdiff | tree
2014-07-28 Clifford WolfAdded wire->upto flag for signals such as "wire [0... commit | commitdiff | tree
2014-07-28 Clifford WolfUsing log_assert() instead of assert() commit | commitdiff | tree
2014-07-28 Clifford WolfAdded std::initializer_list<> constructor to SigSpec commit | commitdiff | tree
2014-07-28 Clifford WolfAdded cover() to all SigSpec constructors commit | commitdiff | tree
2014-07-28 Clifford WolfFixed signdness detection of expressions with bit-... commit | commitdiff | tree
2014-07-28 Clifford WolfImprovements in tests/vloghtb commit | commitdiff | tree
2014-07-27 Clifford WolfAdded techmap -extern commit | commitdiff | tree
2014-07-27 Clifford WolfAdded proper Design->addModule interface commit | commitdiff | tree
2014-07-27 Clifford WolfAdded topological sorting to techmap commit | commitdiff | tree
2014-07-27 Clifford WolfAdded SigPool::check(bit) commit | commitdiff | tree
2014-07-27 Clifford WolfSmall improvements in PerformanceTimer API commit | commitdiff | tree
2014-07-27 Clifford WolfFixed bug in opt_clean commit | commitdiff | tree
2014-07-27 Clifford WolfImproved performance of opt_const on large modules commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpec::remove_const() handling of packed... commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpecConstIterator commit | commitdiff | tree
2014-07-27 Clifford WolfFixed a bug in opt_clean and some RTLIL API usage cleanups commit | commitdiff | tree
2014-07-27 Clifford WolfAdded log_cmd_error_expection commit | commitdiff | tree
2014-07-27 Clifford WolfFixed verific bindings for new RTLIL api commit | commitdiff | tree
2014-07-27 Clifford WolfFixed ilang parser for new RTLIL API commit | commitdiff | tree
2014-07-27 Clifford WolfUsing new obj iterator API in a few places commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::Module::wire(id) and cell(id) lookup functions commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::Design::modules() commit | commitdiff | tree
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ commit | commitdiff | tree
2014-07-27 Clifford WolfAdded conversion from ObjRange to std::vector and std... commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::ObjIterator and RTLIL::ObjRange commit | commitdiff | tree
2014-07-27 Clifford WolfUsing std::move() in SigSpec move constructor commit | commitdiff | tree
2014-07-27 Clifford WolfAdded RTLIL::SigSpec move constructor and move assignme... commit | commitdiff | tree
2014-07-27 Clifford WolfMostly cosmetic changes to rtlil.h commit | commitdiff | tree
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ commit | commitdiff | tree
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ commit | commitdiff | tree
2014-07-26 Clifford WolfNew message for completion of build commit | commitdiff | tree
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors commit | commitdiff | tree
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors commit | commitdiff | tree
2014-07-26 Clifford WolfAdded tests/various/.gitignore commit | commitdiff | tree
2014-07-26 Clifford WolfAdded tests/various/submod_extract.ys commit | commitdiff | tree
2014-07-26 Clifford WolfAdded support for here documents commit | commitdiff | tree
2014-07-26 Clifford WolfMore RTLIL::Cell API usage cleanups commit | commitdiff | tree
2014-07-26 Clifford WolfAdded RTLIL::Cell::has(portname) commit | commitdiff | tree
next