yosys.git
2020-07-23 Marcelina KościelnickaAdd utility module for dealing with init attributes.
2020-07-23 clairexenMerge pull request #2285 from YosysHQ/mwk/techmap-cellname
2020-07-23 clairexenMerge pull request #2294 from Ravenslofty/intel_alm_timings
2020-07-23 Dan Ravensloftintel_alm: add additional ABC9 timings
2020-07-22 Keith RothmanRemove EXPLICIT_CARRY logic.
2020-07-21 Marcelina Kościelnickatechmap: Add _TECHMAP_CELLNAME_ special parameter.
2020-07-21 clairexenMerge pull request #2215 from boqwxp/qbfsat-solver...
2020-07-20 Alberto Gonzalezsmtio: Emit `mode: start` options before `set-logic...
2020-07-20 Alberto Gonzalezsmtio: Add support for parsing `yosys-smt2-solver-optio...
2020-07-20 Alberto Gonzalezqbfsat: Add `-solver-option` option.
2020-07-20 Alberto Gonzalezsmt2: Add `-solver-option` option.
2020-07-20 clairexenMerge pull request #2282 from YosysHQ/claire/satunsat
2020-07-20 Marcelina Kościelnickacelltypes: Fix EN port name for some FF types.
2020-07-20 Claire WolfOnly allow "sat" and "unsat" smt solver responses in...
2020-07-20 clairexenMerge pull request #2276 from YosysHQ/mwk/satgen-cc
2020-07-18 Marcelina Kościelnickasatgen: Move importCell out of the header.
2020-07-17 Miodrag MilanovićMerge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix
2020-07-17 Marcelina Kościelnickasf2: Emit CLKINT even if -clkbuf not passed
2020-07-17 Miodrag MilanovićMerge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
2020-07-17 Marcelina Kościelnickaanlogic: Fix FF mapping.
2020-07-16 clairexenMerge pull request #2229 from Ravenslofty/sf2_remove_sf...
2020-07-16 clairexenMerge pull request #2273 from whitequark/write-verilog...
2020-07-16 clairexenMerge pull request #2272 from whitequark/write-verilog-sv
2020-07-16 Miodrag MilanovićMerge pull request #2238 from YosysHQ/mwk/dfflegalize...
2020-07-16 Miodrag MilanovićMerge pull request #2226 from YosysHQ/mwk/nuke-efinix...
2020-07-16 whitequarkverilog_backend: in non-SV mode, add a trigger for...
2020-07-16 whitequarkverilog_backend: add `-sv` option, make `-o <filename...
2020-07-16 whitequarkMerge pull request #2270 from whitequark/cxxrtl-fix...
2020-07-15 whitequarkMerge pull request #2269 from YosysHQ/claire/bisonwall
2020-07-15 Claire WolfTreat all bison warnings as errors in verilog front-end
2020-07-15 Claire WolfUse %precedence in verilog_parser.y
2020-07-15 Claire WolfFix bison warnings for missing %empty
2020-07-15 Claire WolfRun bison with -Wall for verilog front-end
2020-07-15 clairexenMerge pull request #2257 from antmicro/fix-conflicts
2020-07-15 Kamil RakoczyAdd missing semicolons
2020-07-15 Marcelina Kościelnickaopt_merge: Dedup one more use of FF cell type list.
2020-07-14 Marcelina Kościelnickaachronix: Use dfflegalize.
2020-07-14 whitequarkcxxrtl: fix typo. NFC.
2020-07-14 Marcelina Kościelnickaanlogic: Use dfflegalize.
2020-07-13 Marcelina Kościelnickaintel: Use dfflegalize.
2020-07-13 LoftyRevert "intel_alm: direct M10K instantiation"
2020-07-13 whitequarkMerge pull request #2263 from whitequark/cxxrtl-capi...
2020-07-12 whitequarkcxxrtl: expose eval() and commit() via the C API.
2020-07-12 Marcelina Kościelnickaxilinx: Fix srl regression.
2020-07-12 Marcelina Kościelnickaproc_dlatch: Remove init values for combinatorial proce...
2020-07-12 Marcelina Kościelnickadfflegalize: Gather init values from all wires.
2020-07-10 clairexenMerge pull request #2256 from YosysHQ/claire/fix2241
2020-07-10 Claire WolfAdd AST_EDGE support to AstNode::detect_latch(), fixes...
2020-07-10 Kamil RakoczyFix S/R conflicts
2020-07-10 Kamil RakoczyFix R/R conflicts
2020-07-10 Kamil RakoczyRevert "Revert PRs #2203 and #2244."
2020-07-09 Dan Ravensloftsf2: replace sf2_iobs with {clkbuf,iopad}map
2020-07-09 whitequarkMerge pull request #2255 from whitequark/bison-Werror...
2020-07-09 whitequarkMerge pull request #2254 from whitequark/cxxrtl-extern-c
2020-07-09 Marcelina Kościelnickasf2: Use dfflegalize.
2020-07-09 whitequarkverilog_parser: turn S/R and R/R conflicts into hard...
2020-07-09 whitequarkRevert PRs #2203 and #2244.
2020-07-09 whitequarkcxxrtl: add missing extern "C".
2020-07-09 Marcelina Kościelnickaxilinx: Use dfflegalize.
2020-07-09 Marcelina Kościelnickadfflibmap: Refactor to use dfflegalize internally.
2020-07-09 Lucas CastroFix issue #2251 (#2252)
2020-07-09 Marcelina Kościelnickaclkbufmap: improve input pad handling.
2020-07-09 clairexenMerge pull request #2244 from antmicro/logic
2020-07-09 Marcelina Kościelnickaclk2fflogic: Consistently treat async control signals...
2020-07-09 Marcelina Kościelnickadfflegalize: Add special support for const-D latches.
2020-07-07 whitequarkMerge pull request #2246 from YosysHQ/mwk/dfflegalize...
2020-07-07 Marcelina Kościelnickadfflegalize: typo fix
2020-07-06 Marcelina Kościelnickaefinix: Use dfflegalize.
2020-07-06 Marcelina Kościelnickagowin: Use dfflegalize.
2020-07-06 Kamil RakoczyAdd logic param and integer bad syntax tests
2020-07-06 Lukasz DalekSupport logic typed parameters
2020-07-05 Dan Ravensloftintel_alm: direct M10K instantiation
2020-07-05 Marcelina KościelnickaNaming fixes.
2020-07-05 Dan Ravensloftsynth_gowin: ABC9 support
2020-07-05 Dan Ravensloftintel_alm: add Cyclone 10 GX tests
2020-07-05 Marcelina KościelnickaMerge pull request #2236 from YosysHQ/mwk/dfflegalize...
2020-07-05 Marcelina Kościelnickaecp5: Use dfflegalize.
2020-07-05 whitequarkMerge pull request #2227 from Ravenslofty/ccache
2020-07-05 Marcelina KościelnickaMerge pull request #2232 from YosysHQ/mwk/gowin-sim...
2020-07-05 Marcelina Kościelnickadfflegalize: Prefer mapping dff to sdff before adff
2020-07-05 Marcelina Kościelnickaopt_expr: Fix crash on $mul optimization with more...
2020-07-05 Dan Ravensloftintel_alm: DSP inference
2020-07-05 Marcelina Kościelnickaice40: Use dfflegalize.
2020-07-05 Marcelina Kościelnickagowin: Fix INIT values in sim library.
2020-07-04 Dan Ravensloftgowin: replace determine_init with setundef
2020-07-04 Marcelina Kościelnickasynth_intel_alm: Use dfflegalize.
2020-07-04 Dan RavensloftAdd option to use ccache when building
2020-07-04 Marcelina Kościelnickaefinix: Nuke efinix_gbuf in favor of clkbufmap.
2020-07-04 Dan RavensloftImprove MISTRAL_FF specify rules
2020-07-04 Eddie Hungtests: update fsm.ys resource count
2020-07-04 Eddie Hungabc9: only techmap (* abc9_flop *) modules
2020-07-04 Eddie Hungintel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
2020-07-04 Eddie Hungabc9: techmap from user design to allow abc9_flop modul...
2020-07-04 Eddie Hungintel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
2020-07-04 Dan Ravensloftintel_alm: ABC9 sequential optimisations
2020-07-03 Rupert SwarbrickAdd newlines to help text for dfflegalize
2020-07-02 clairexenMerge pull request #2132 from YosysHQ/eddie/verific_initial
2020-07-02 clairexenMerge pull request #2208 from boqwxp/qbfsat-cleanup
2020-07-02 clairexenMerge pull request #2186 from YosysHQ/mwk/dfflegalize
2020-07-02 clairexenMerge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
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